適用於通訊系統之內嵌式數位訊號處理器

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姓名

李曉屏(Hsiao-Ping Lee ) 查詢紙本館藏

畢業系所

電機工程研究所

論文名稱

適用於通訊系統之內嵌式數位訊號處理器
(An Embedded DSP Core for Communication Applications)

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摘要(中)

在本篇論文中，實現了一顆十六位元的可程式化數位信號處理器。它是專用於通訊系統應用。除了提供一般十六位元數位處理器所具備的基本指令集外，還為了特別的功能硬體設計，提供特殊指令。這使得這顆數位信號處理器更適於計算密集的應用。
我們所提出的數位信號處理器具有幾項優越的特性: 可參數化的架構，高速的效能，和低功率。我們設計了各種模組產生器以產生可變動(configurable)的資料路徑(dat apath)和可重複使用的特殊功能硬體。平行化的架構也加速了效能，在效能測試程式中兩組乘法器串聯加法器減少一半的指令週期。為了減少功率耗損，我們採用許多種低功率設計技巧，如灰碼記憶體定址法和管線分享技巧等。
這顆數位信號處理器的最大工作效能可操作在每秒100百萬指令之

摘要(英)

In this thesis, the design and implementation a programmable 16-bit Digital signal processing (DSP) processor are carried out. It is developed specifically for a communication system. Besides providing a basic instruction set, similar to current day 16-bit DSP processors, it contains unique instructions, extra architecture features and special function blocks, which make this DSP processor more efficient for compute-intensive tasks.
The proposed DSP processor has some advanced features: a parameterized architecture, high-speed performance, and low power. So various module generators are designed to generate configurable datapath and reusable special function blocks. In addition, we use high degree of parallelism to speed up its performance. The data path contains two Multiply-Accumulate units to reduce half instruction cycles in the performance benchmarks. To reduce power consumption, we use some low power designs such as gray code memory addressing, pipeline sharing techniques.
The chip was implemented in a cell-base design method using a 0.35 1P3M cell-library. The maximum performance of NCU_DSP is 100MHz.

關鍵字(中)

★ 低功率
★ 可參數化
★ 數位信號處理器
★ 通訊系統應用
★ 高速的效能

關鍵字(英)

★ communication systems
★ Digital signal processing processor
★ high performance
★ low power
★ parameterized

論文目次

Content
CHAPTER 1 INTRODUCTION1
1.1 Motivation1
1.2 Evolution of Communication DSP Processors3
1.3 Applications-Specific DSP For Communication and Embedded System5
1.4 Thesis Organization7
CHAPTER 2 ARCHITECTURE OF DSP CORE8
2.1 The Overview of NCU_DSP Architecture8
2.2 Program Address Generation Unit8
2.2.1 A Basic Operation of Program Address Generation8
2.2.2 Hardware Looping9
2.2.3 Conditional/Unconditional Branches, Calls and Returns12
2.2.4 The Analysis of Synthesis Result15
2.3 Data Address Generation Unit15
2.3.1 The Analysis of Synthesis Result19
2.3.2 Summary……………………………………………………….20
2.4 Memory Architecture20
2.5 Computational Unit21
2.5.1 Data path 21
2.5.2 Application-Specific Function Blocks23
2.6 Parameterized DSP Core23
2.7 Summary24
CHAPTER 3 INSTRUCTION SETS26
3.1 Introduction26
3.2 Design of Instruction Sets26
3.3 Instruction Types27
3.3.1 Arithmetic and Logic Operation28
3.3.2 Shifting and Comparisons28
3.3.3 Program Flow Control29
3.3.4 Special Function Instructions29
3.4 NCU_DSP's Instruction Sets vs. TIC54x's30
3.5 Summary32
CHAPTER 4 PIPELINE ARCHITECTURE OF DATA PATH33
4.1 Introduction33
4.2 Unconditional Branch Operation In The Pipeline39
4.3 Conditional Branch Instructions In The Pipeline Operation40
4.4 Pipeline Hazards43
4.4.1 Control Hazards43
4.4.2 Structure Hazards44
4.4.3 Data Hazards and Forwarding45
CHAPTER 5 LOW POWER DESIGNS48
5.1 Low Power Architecture48
5.2 Gray Coded Addressing49
5.3 Pipeline Sharing51
5.4 Variable Word Instruction Set (VLIS)53
5.5 Summary54
CHAPTER 6 CHIP IMPLEMENTATION AND SIMULATION RESULTS55
6.1 Design Flow55
6.2 Synthesis Result55
6.3 Place and Rout Result57
6.4 Benchmarks Simulation58
6.4.1 FIR Filter58
6.4.2 Square Distance60
6.4.3 Inner Hardware Looping61
6.5 Comparison61
CHAPTER 7 CONCLUSIONS63
Appendix A: Instruction Sets64
References …..………………70

參考文獻

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指導教授

周世傑(Shyh-Jye Jou)

審核日期

2001-7-6

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