通訊應用之內嵌式數位訊號處理器核心產生器

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姓名

陳威豪(Wei-Hao Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

通訊應用之內嵌式數位訊號處理器核心產生器
(Module Generator of Embedded DSP Core for Communication Applications)

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摘要(中)

在本篇論文中，實現了一個可參數化的內嵌式數位信號處理器系統— NCU_DSP_2003。它是由去年的NCU_DSP_2002核心增進而來的。它能偵測出資料危障(data hazard)和結構危障(structure hazard)且做資料前移動作使硬體正常工作。而為了加快DSP演算和減少功率耗損，我們改進了有關原本的迴圈指令和增加一個新的迴圈指令，使得這顆數位信號處理器更適用於計算有迴圈密集的應用上。
我們所提出的可參數化數位信號處理器設計流程具有幾項優越的特性：可參數化的架構，可選擇式特殊應用硬體，低功率及為內嵌式應用之I/O設計。我們設計了各種模組產生器以產生可變動(configurable)的資料路徑(datapath)和可重複使用的特殊功能硬體。還有我們提供了三種乘法器模組供使用者依實際使用上的需要做選擇。並設計了一個模組產生器用以整合各個功能模組及產生數位信號處理器的硬體描述語言。
以模組產生器所產生的十六位元數位信號處理器為例，其最大工作效能可操作在170百萬指令。

摘要(英)

This thesis introduces the design and implementation of an embedded and parameterized digital signal processing (DSP) processor---NCU_DSP_2003. it is an enhanced version of last year version---NCU_DSP_2002. Besides providing a basic instruction set that is similar to conventional DSP processors, the enhanced capabilities include detector of the data hazard and structure hazard and do data forwarding. To enhance the operation of DSP and reduce power consumption, it provides two kinds of the nested loop instruction. These improvements make this DSP processor more efficient for computation-intensive application.
The proposed parameterized DSP processor design system has some advanced features: a parameterized architecture, special functions for communication application, some low power designs and I/O for embedded consideration. We provide three kinds of Multiply-Accumulate unit for user to select according to practical applications. By using window GUI and a Verilog code generator, dedicated DSP for specified application can be generated.
The chip will be implemented in a cell-based design method with a 0.25 1P5M cell library. The maximum operating frequency of a 16?16 DSP is about 170MHz.

關鍵字(中)

★ 模組產生器
★ 數位訊號處理器
★ 通訊應用

關鍵字(英)

★ DSP
★ parameterized
★ module generator

論文目次

Content
CHAPTER 1 INTRODUCTION……………………………………………………...1
1.1 Motivation…………………………………………………………………...1
1.2 Goal and Applications……………………………………………………….4
1.3 Thesis Organization………………………………………………………….6
CHAPTER 2 THE ARCHITECTURE OF NCU_DSP_2003………………….……...7
2.1 The Overview of NCU_DSP_2003 Architecture……………………………7
2.2 Program Address Generation Unit (PAGU)………………………………..10
2.2.1 Hardware Looping…………………………………………………..12
2.2.2 Hardware Buffer Looping…………………………………………..15
2.3 Hazard and Solution………………………………………………………..18
2.3.1 Data Forwarding…………………………………………………….20
2.3.2 Memory Structure Hazard and Solution…………………………….25
2.4 Data path…………………………………………………………………...26
2.4.1 Modify Barrel Shifter Location……………………………………..27
2.4.2 MAC………………………………………………………………...28
2.2 I/O Synchronization………………………………………………………..32
CHAPTER 3 PARAMETERIZED DESIGN FLOW AND IMPLEMENTATION….34
3.1 Introduction……………………………………………………………….34
3.2 Parameter of NCU_DSP_2003 Generator………………………………...35
3.3 Special Function Block of NCU_DSP_2003 Generator………………….37
3.4 Parameterized and Configurable Architecture Flow....…………………...40
3.5 Generator Architecture................................................................................45
CHAPTER 4 Design and Implement Results………………….…………………….47
4.1 Synthesis Results…………………………………………….…………....47
4.1.1 NCU_DSP_2003---Hardware Looping……………....……………..48
4.1.2 NCU_DSP_2003---Hazard and Solution…………………………...50
4.1.3 NCU_DSP_2003---Datapath………………………………………..51
4.2 Design Case…………………………………………………………….....52
4.3 Benchmark Simulation and Features……………………………………...54
CHAPTER 5 CONCLUSIONS AND FUTURE WORK…………………………….56
REFERENCE………………………………………………………………………...57

參考文獻

Reference
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指導教授

周世傑(Shyh-Jye Jou)

審核日期

2003-7-7

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