適用於第三代行動通訊之最大事後機率演算法發展及渦輪碼解碼器超大型積體電路設計

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姓名

林承鴻(Cheng-Hung Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於第三代行動通訊之最大事後機率演算法發展及渦輪碼解碼器超大型積體電路設計
(Development of MAP Algorithm and VLSI Design of Turbo Decoding for 3GPP)

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摘要(中)

渦輪碼已經是近年來通道編碼理論的一項重大突破。而在渦輪解碼裡軟式輸入軟式輸出解碼演算法中，以最大事後機率演算法最強而有力。然而，最大事後機率演算法解碼器在硬體實現上需要大量的記憶體，因此，本論文提出一種創新的最大事後機率解碼器架構，根據渦輪碼時間對應計算排成圖的分析，後向反覆運算可以直接地被轉換與前向反覆運算同時同向處理，它並可以有效地減少記憶體單元與面積。從比較結果中，更可看出它比起以往的研究更有效地減少到一半的記憶體存儲量。除此之外，提出的架構不像以往的研究，它簡化了記憶資料存取的動作，而不需要其他額外的位址產生器。
另外，渦輪碼中最大事後機率解碼演算法有一個訊息上的要求，這訊息上的要求是通道訊號雜訊比。若解碼端與實際通道訊號雜訊比發生不一致，渦輪解碼的錯誤更正能力便會被減低。因此在本論文中，一種結合了過去研究中所發表出來早終結技術的低複雜度通道估計演算法被提出來，早終結技術是用來減少渦輪碼中遞迴數的技術。其中，兩種早終結技術：硬式決定和軟式決定條件被模擬在通道訊號雜訊比不一致的情況之下。藉由模擬的結果通道估計演算法被提出來，其擁有了減少渦輪碼遞迴數和容易實現的兩個優點。在2分貝的實際訊號雜訊比條件下，與分析在最大遞迴數20相比，結果顯示渦輪解碼只用3個遞迴數便可被早終結技術終止；根據我們的模擬結果，在位元錯誤率為10-5的情況下，幾個框架解碼後，提出的方法就可以估計可靠的通道訊號雜訊比以提煉更正效能，與完全已知真實訊號雜訊比相比，只有0.1分貝的編碼增益失真。
在UMC .18um 1p6m CMOS 製程中，一顆根據3GPP標準以超大型積體電路設計之渦輪解碼器被實現在核心面積為3.7 x 3.7平方公釐的原型晶片內，以驗證所提出渦輪解碼器的架構，其最大操作頻率可達到149 MHz。在3GPP標準且最大遞迴數為6的情況下，提出的渦輪解碼器可以得到12 Mb/s 解碼率當頻率操作在149 MHz時。

摘要(英)

In coding theory, turbo codes have been the breakthrough in recent years. Among these, the maximum a posteriori (MAP) probability algorithm is a powerful soft-input soft-output (SISO) algorithm for turbo decoding. However, MAP decoders of the turbo decoding consume large memories in hardware implementation. This thesis presents a new architecture for memory reduction in log-MAP (logarithm-MAP) algorithm. Based on the scheduling analysis, the backward recursion can be reversed in order to be directly operated on with forward recursion. The comparison result shows it can effectively reduce the memory size up to half size of the previous works. In addition, we also simplify the memory data access without an extra address generator.
Moreover, one requirement of iterative MAP decoding of turbo codes is the knowledge of the channel SNR. The correction ability of turbo decoding is degraded by mismatch of channel SNR. In this thesis, a low complexity channel estimation algorithm based on early termination techniques used to reduce the number of iterations is proposed. Both of the hard and soft decisions for early termination techniques are simulated with SNR mismatch. Our algorithm takes the advantages of reducing the iterations and easy implementation on channel estimation. Only 3 iterations can be achieved compared with the analyzed 20 iterations at 2-dB true SNR. Based on our simulation results, the proposed method can practically estimate the reliable channel SNR to refine the correction performance after several frames, and get 0.1-dB coding gain loses compared to true channel SNR at BER = 10-5.
A prototyping chip is implemented to verify the proposed architecture in 3.7×3.7mm2 die area, and the clock frequency is 149MHz in UMC 0.18um 1p6m CMOS process. For 3GPP standard, the proposed decoder can obtain 12Mb/s decoding rate when operating at 149 MHz with 6 iterations.

關鍵字(中)

★ 第三代行動通訊
★ 最大事後機率演算法
★ 渦輪碼
★ 超大型積體電路

關鍵字(英)

★ VLSI
★ 3GPP
★ Turbo Codes
★ MAP

論文目次

Abstract………………………………………………………………………………. i
Content……………………………………………………………………………….. ii
List of Figures……………………………………………………………………….. iv
List of Tables………………………………………………………………………… vi
Chapter 1 Introduction………………………………………………………….. 1
1.1 Motivation…………………………………………………………….. 1
1.2 Implementation Overview…………………………………………….. 3
1.3 Thesis Organization…………………………………………………… 5
Chapter 2 Fundamentals of Turbo Codes……………………………………… 6
2.1 Turbo Encoder………………………………………………………… 6
2.2 Turbo Decoder………………………………………………………… 9
2.3 Log-MAP Algorithm………………………………………………… 16
Chapter 3 Memory-Reduced Log-MAP Subdecoders……………………….. 19
3.1 Classical Architecture………………………………………………... 20
3.2 Recomputed Architectures…………………………………………... 21
3.2.1 Recomputed-1 Architecture…………………………………... 21
3.2.2 Recomputed-2 Architecture…………………………………... 23
3.3 Proposed Architecture……………………………………………….. 24
3.4 Analysis Results……………………………………………………... 27
3.5 Advanced Approach…………………………………………………. 31
Chapter 4 Proposed Channel Estimation Algorithm with Early Termination Techniques………………………………………………………… 33
4.1 Early Termination Techniques……………………………………….. 34
4.2 SNR Sensitivity……………………………………………………… 35
4.3 Proposed Algorithm and Architecture Design……………………….. 38
Chapter 5 VLSI Design of The Proposed Turbo Decodes for 3GPP Standards…………………………………………………………. 44
5.1 Turbo Codes in 3GPP Standard……………………………………… 45
5.1.1 Turbo Coding…………………………………………………. 45
5.1.2 Trellis Termination……………………………………………. 45
5.1.3 Internal Interleaving…………………………………………... 46
5.2 Architecture Design………………………………………………….. 48
5.2.1 Overall Architecture…………………………………………... 48
5.2.2 Log-MAP Subdecoder…………………………………………49
5.2.3 Linked State Machine………………………………………… 51
5.2.4 Rescaling……………………………………………………… 52
5.2.5 Channel Estimation…………………………………………… 53
5.2.6 Technical Specification……………………………………….. 53
5.3 IC Design Flow……………………………………………………… 57
5.4 Implementation Results……………………………………………… 57
5.4.1 MATLAB Simulation Results………………………………… 58
5.4.2 Chip Layout…………………………………………………... 60
5.5 Comparisons…………………………………………………………. 61
Chapter 6 Conclusions…………………………………………………………. 64
Reference……………………………………………………………………………. 66

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指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2004-7-12

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