寬頻劃碼多工進接接收機之射頻前端電路研製

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姓名

蔡志育(Chih-Yu Tsai) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

寬頻劃碼多工進接接收機之射頻前端電路研製
(The Study of RF Front-End Circuits for WCDMA Receiver)

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摘要(中)

摘要
本論文採用台積電0.35微米矽鍺雙載子互補金屬氧化半導體製程，實現寬頻劃碼多工進接接收機之射頻前端電路；論文內容分成接收機系統之規格分析與電路設計兩部分，其中第二章為寬頻劃碼多工進接接收機系統之設計規劃，根據3GPP規範與測試標準，推導出射頻接收機之系統規格：雜訊指數<8.7dB，相鄰頻道靈敏度>34dB，輸入二階截取點>-15dBm，輸入三階截取點>-16.8dBm，在與振盪頻率距8MHz的相位雜訊<-129dBc/Hz。
第二部分的接收機之射頻前端電路設計為主要研究內容，包含低雜訊放大器、混波器、壓控振盪器與除頻器，以下將概述各電路之實際量測結果：
第三章為微混波器設計，其量測結果轉換增益8dB，輸入1dB壓縮點為-12dBm，輸入三階截取點為2dBm，所有埠之間的訊號隔離度皆大於23dB，中頻頻寬為150MHz。
第四章為差動式可變增益低雜訊放大器，其量測結果增益16.5dB，雜訊指數為2.1dB，輸入1 dB壓縮點為-15dBm，輸入三階截取點為-2dBm，增益控制範圍為11dB。
第五章為全對稱差動式可變增益接收機，其量測結果轉換增益16dB，雜訊指數為3.2dB，輸入1 dB壓縮點為-30dBm，輸入二階截取點為25dBm，輸入三階截取點為-17dBm，所有埠之間的訊號隔離度皆大於32dB，增益控制範圍為11dB。
第六章為雙端考畢茲壓控振盪器與除頻器的設計，其中2.15GHz振盪器量測結果為相位雜訊-97.3dBc/Hz，輸出功率為-9dBm，可調頻率範圍為225MHz；4.3GHz振盪器與除頻器量測結果為相位雜訊-94.6dBc/Hz，輸出功率為-6dBm，可調頻率範圍為379MHz，除頻器輸出功率為-8.58dBm。

摘要(英)

Abstract
In this work, RF front-end circuit for WCDMA receiver is implemented by using tsmc SiGe 0.35?m BiCMOS process. This thesis is divided into two parts which are the analysis system-level specifications of WCDMA receiver and front-end circuits design. The first part is described in chapter 2, The detail derive of the receiver requirements according to the 3GPP specifications and standard testing are introduced. The required specifications are as following: NF<8.7dB, Adjacent-Channel Selectivity>34dB, IIP2>-15.6dBm, IIP3>-16.8dBm and Phase Noise<-129dBc @ 8MHz offset.
The second part of RF front-end circuit for WCDMA receiver is the main research in this thesis, such as low noise amplifier, micromixer, voltage-controlled oscillator and frequency divider designs. Following are the measured results of these designs.
Chapter 3 is micromixer design and the measurements of conversion gain is 8dB, input power at the 1-dB gain compression point is -12dBm, input third-order intercept point is 2dBm, all port-to-port isolations are greater than 23dB and IF bandwidth is 150MHz.
Chapter 4 is the design of differential variable gain LNA and the measurements of gain is 16.5dB, noise figure is 2.1dB, input power at the 1-dB gain impression point is -15dBm, input third-order intercept point is -2dBm and gain control range is 11dB.
Chapter 5 is the design of fully differential variable gain receiver and the measurements of conversion gain is 16dB, noise figure is 3.2dB, input power at the 1-dB gain impression point is -30dBm, input second-order intercept point is 25dBm, input third-order intercept point is -17dBm, all port-to-port isolation is greater than 32dB and gain control range is 11dB.
Chapter 6 is the design of differential Colpitts VCO and frequency divider, the measurements of 2.15GHz VCO are as following: phase noise: -97dBc/Hz @100KHz offset, output power: -9dBm and tuning range: 225MHz. The measurements of 4.3GHz VCO and frequency divider are following: phase noise: -94.6dBc/Hz @100KHz offset, output power: -6dBm, tuning range: 379MHz and divider output power is -8.58dBm.

關鍵字(中)

★ 寬頻劃碼多工進接
★ 射頻接收機
★ 矽鍺雙載子互補金屬氧化半導體製程

關鍵字(英)

★ RF Receiver
★ SiGe BiCMOS process
★ WCDMA

論文目次

Abstract ……………………………………………………………………………ii
Content ………………………………………………………………………………v
List of Figures …………………………………………………………………vii
List of Tables ……………………………………………………………………x
Chapter 1 Introduction 1
1-1 Motivation 1
1.2 Thesis Overview 1
Chapter 2 System Specifications of WCDMA Receiver 3
2.1 System Overview 3
2.2 Receiver Architecture 3
2.3 Analysis of the System-Level Specifications 5
2.3.1 Noise Figure 8
2.3.2 Dynamic Range 9
2.3.3 Adjacent-Channel Selectivity 9
2.3.4 Second-Order Intercept Point 9
2.3.5 Third-Order Intercept Point 11
2.3.6 Phase Noise 12
2.4 Conclusion 14
Chapter 3 Design of the Fully Integrated Micromixer 15
3.1 Introduction 15
3.2 Circuit Design and Implementation 16
3.3 Measurements 19
3.4 Discussion and Conclusion 26
Chapter 4 Design of the Differential Variable Gain LNA 27
4.1 Introduction 27
4.2 Circuit Topology and Theory 27
4.3 Circuit Design and Implementation 32
4.3.1 Design Concept 32
4.3.2 Gain-Controlled Mechanism 33
4.4 Measurement 34
4.5 Discussion and Conclusion 43
Chapter 5 Design of the Fully Differential Variable Gain Receiver 44
5.1 Introduction 44
5.1.1 Heterodyne Receiver 44
5.1.2 Direct-Conversion Receiver 45
5.1.2.1 DC Offset 46
5.1.2.2 Even-Order Distortion 48
5.1.2.3 Flicker Noise 48
5.1.2.4 I/Q Mismatch 49
5.1.2.5 LO Radiation 49
5.2 Circuit Topology and Theory 50
5.3 Circuit Design and Implementation 50
5.3.1 Design Concept 50
5.3.1 Gain-Controlled Mechanism 51
5.4 Measurement 52
5.5 Discussion and Conclusion 61
Chapter 6 Design of the Differential Colpitts VCO 63
6.1 Introduction 63
6.1.1 Oscillator Theory 64
6.1.2 Linear Time-Invariant Theory 65
6.1.3 Linear Time-Varying Theory 66
6.2 Differential Colpitts VCO 71
6.2.1 Circuit Topology and Theory 71
6.2.2 Circuit Design and Implementation 73
6.2.3 Measurement 75
6.2.4 Discussion and Conclusion 80
6.3 4.3GHz Differential Colpitts VCO and Divider 84
6.3.1 Circuit Topology and Theory 84
6.3.2 Circuit Design and Implementation 86
6.3.3 Measurement 89
6.3.4 Discussion and Conclusion 94
Chapter 7 Conclusions and Future Works 95
References 97

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指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2005-7-19

推文