參考文獻 |
參考文獻資料
[1] William D.Brown ,Joe E.Brewer,”Nonvolatile Semiconductor Memory
Technology”,The institute of Electrical and Electronics Engineers Inc,1997.
[2] Stefan Lai, ”Tunnel Oxide and ETOX Flash scaling Limitation”, Intel
Non Volatile Memory Technology conference, 1998.
[3] J. J. Welser et al., “Room temperature operation of a quantum-dot flash memory,”IEEE Electron Device Letters, EDL-18, p.278, 1997
[4] B. H. Choi et al., “Fabrication and room-temperature characterization of a silicon self-assembled quantum dot transistor,” Appl. Phys. Lett., 73, p.3129, 1998
[5] T. Baron et al., “Chemical vapor deposition of Ge nanocrystls on SiO2,” Appl. Phys.Lett., 83, p.1444, 2003
[6] H. Ishikuro et al., “Quantum mechanical effects in the silicon quantum dot in a single-electron transistor,” Appl. Phys. Lett, 71, p.3691, 1997
[7] S. Tiwari, et al., “Volatile and nonvolatile memories in silicon with nanocrystal storage,” IEEE IEDM Technical Digest, p.521, 1995
[8] S. Tiwari, et al., “Single electron charging of Sn nanocrystals in Thin SiO2 film formed by low energy ion implantation,” IEEE IEDM Technical Digest, p.159, 1997
[9] C. Y. King et al., “MOS memory using germanium nanocrystals formed by thermal oxidation of SiGe,” IEEE IEDM Technical Digest, p.115, 1998
[10] W. K. Choi et al., “Observation of memory effect in germanium nanocrystals embedded in an amorphous silicon oxide matrix of a metal-insulator-semiconductor structure,” Appl. Phys. Lett., 80, p.2014, 2002
[11] R. Ohba, et al., “Nonvolatile Si quantum memory with self-aligned doubly-stacked dots,” IEEE Trans. Electron Devices, 49, 1392, 2002
[12] Y. Shi, et al., “Effects of interface traps on charge retention characteristics in silicon-quantum-dot-based metal-oxide-semiconductor diodes,” Jpn. J. Appl. Phys., 38, 425, 1999]
[13] Mori, N. Arai, Y. Kaneko and K. Yoshikawa, “Polyoxide Thinning
Limitation and Superior ONO Interpoly Dielectric for Nonvolatile Memory
Device” ,IEEE Transactions on Electron Device , Vol. 38,NO.2,FEB, 19
[14] Mori, E. Sakagami, H. Araki, Y. Kaneko, K. Narita, Y.Ohshima, N. Arai
and K. Yoshikawa, ”ONO Inter-poly Dielectric Scaling for Nonvolatile
Memory Applications”, IEEE Transactions on Electron
Device ,Vol.38,NO.2,FEB, 1991.
[15] S. Tam, P. K. Ko, and C. Hu, “Lucky-Electron Model of Channel
Hot-Electron Injection in MOSFET’s,” IEEE Transaction on
Electron Devices, Vol.31, September 1984, p.1116.
[16] M. Lenzlinger and E. H. Snow, “Fowler-Nordheim Tunneling into
Thermally Grown SiO2,” Journal of Applied Physics, January 1969, p.278.
[17] Pan, K. Wu, P. Freiberger, A.Chatterjee, G. Sery,” A Scaling Methodology for Oxide-Nitride-Oxide Interpoly Dielectric for EPROMApplication”, IEEE Trans. on Electron Dev. Vol.37, No.6, P.1439, Jun. 1990.
[18] Pan, K. Wu , D. Chin, G. Sery, J. Kiely,” High-Temperature Charge Loss
Mechanism in Floating-Gate EPROM with an Oxide-Nitride-Oxide(ONO)
Interpoly Stacked Dielectric”,IEEE Electron Dev.Lett.,
Vol.12,No.9,P.506,Sep.1991.
[19] T. Hiramoto, H. Ishikuro and T. Fujii, “Fabrication of Si nanostructures for
Single-Electron device Applications by Anisotropic etching”, Jpn. J. Appl. Phys., vol.35, p6664, 1996
[20] Tsu-Jae King and Krishna C. Saraswat, “Deposition and Properties of Low-Pressure Chemical-Vapor Deposited Polycrystalline Silicon-Germanium Film”,Department of Electrical Engineering, Stanford University Stanford, California 94305 |