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姓名	羅有龍(Yu-Lung Lo)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	互補式金氧半高性能與低電壓時脈同步電路之設計及實作 (Design and Implementation of CMOS High-Performance Low-Voltage Clock Synchronization Circuits)
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摘要(中)	隨著矽製程技術的演進，晶片的尺寸與速度的增加，相位及時脈誤差的問題變的相當地重要，尤其在單晶片系統設計上。而延遲鎖定迴路及鎖相迴路為時脈同步電路，廣泛地應用在微處理器、記憶體介面及通訊晶片上，用來解決訊號間的時脈誤差與抖動問題。而本論文主要是敘述延遲鎖定迴路及鎖相迴路之設計及實作。 在第二章中，我們利用粗調的技巧來實現一個具快速鎖定的延遲鎖定迴路。所提出的粗調電路與電源重置電路可以用來克服傳統延遲鎖定迴路所發生的錯誤鎖定問題，並可以提供較快的鎖定時間。此外，所提出的壓控延遲線可以減少動態開關所造成的功率與雜訊。而提出的快速鎖定的延遲鎖定迴路是以0.35-微米的互補式金氧半製程製造，可以正確的操作在100至190百萬赫茲，並可在一個週期產生均等分的八個相位輸出，最大的鎖定時間為43個時脈週期。當輸入頻率為190百萬赫茲時，所量測的方均根抖動及峰值抖動分別是8.463微微秒及46微微秒，其功率消耗為39.6毫瓦，其中包含消耗在輸入及輸出緩衝器的部份。 在第三章中，我們提出利用頻率選擇器來實現一個具寬頻操作的延遲鎖定迴路。所提出的頻率選擇器與多段式控制的壓控延遲線，可使延遲鎖定迴路有更寛的操作頻率範圍與低抖動的性能，並且利用數位式控制的充電泵可使延遲鎖定迴路具有可調性頻寛的功能。而提出的寬頻操作的延遲鎖定迴路是以0.25-微米的互補式金氧半製程製造，主要的電路面積為0.32×0.22平方毫米，其中迴路濾波器的電容約佔面積的50%。操作頻率範圍是從32至320百萬赫茲，並可以在一個週期產生均等分的十個相位輸出，所量得的靜態相位誤差在50百萬赫茲及200百萬赫茲時，分別為22微微秒與9.9微微秒。當輸入頻率為200百萬赫茲時，所量測的方均根隨機性抖動及峰值定量性抖動分別是4.44微微秒及15微微秒。 在第四章中，我們提出了一個可以應用在頻率合成器上的高速超低電壓操作的除四/除五計數器。我們將所提出的動態浮接輸入正反器與邏輯閘化簡合併以減少節點上的有效電容來提升整體操作速度。而提出的高速超低電壓操作的除四/除五計數器是以0.13-微米的互補式金氧半製程製造，其電路面積為21×9平方微米。當供應電壓為0.5伏特，在除四的模式，所量到的最大操作頻率是600百萬赫茲，其功率消耗為8.35微瓦。在電壓低於1伏特時，所提出的除四/除五計數器與傳統的作比較，我們所提出的除四/除五計數器具有最小的功率延遲乘積。 在第五章中，我們提出利用基體輸入的壓控震盪器來實現一個具超低電壓操作的鎖相迴路。當操作電壓低至0.5伏特時，所提出的鎖相迴路利用基體輸入與順向基體偏壓的技巧來克服臨界電壓的問題，並且成功地證明可以應用在太陽能電池上。此超低電壓操作的鎖相迴路是以0.13-微米1.2伏特的互補式金氧半製程製造，其電路面積為0.04平方毫米。在操作電壓為0.5伏特的太陽能電池時(峰值電源雜訊為59毫伏特)，操作頻率可以達到550百萬赫茲，其功率消耗為1.25毫瓦，所量得的方均根抖動及峰值抖動分別是8.76微微秒及67.27微微秒。
摘要(英)	As silicon fabrication technology develops, chip size and operating frequency increase, the problems of phase error and clock skew become extremely important, especially in system-on-a-chip (SoC) design. Delay-locked loops (DLLs) and phase-locked loops (PLLs) are clock synchronization circuits that widely adopted to solve clock signal skews and jitters in microprocessors, memory interfaces and communication IC’s. This thesis mainly describes the design and implementation of DLLs and PLLs. In chapter 2, a fast-lock delay-locked loop with coarse tune technique is proposed. The coarse tune circuit and POR circuit are proposed to overcome the problems of the false locking associated with conventional DLLs and offer the faster locking time. Moreover, the proposed VCDL can reduce dynamic switching power dissipation and noise. An experimental chip is designed and fabricated based on a 0.35-μm single-poly four-metal CMOS process. The proposed DLL can operate correctly from 100 to 190MHz and generate equally spaced eight-phase clocks. The locking time is less than 43 clock cycles. When the input clock frequency is 190MHz, the measured output clock rms jitter and peak-to-peak jitter are 8.463ps and 46ps, respectively. The power consumption is 39.6mW at 190MHz including the portion consumed by input and output digital buffers. In chapter 3, a wide-range delay-locked loop with frequency range selector is proposed. The proposed frequency range selector and multi-controlled delay cell for the voltage-controlled delay line are applied to provide the wide operating frequency range and low-jitter performance. The charge pump circuit is implemented using a digital control scheme to achieve adaptive bandwidth. The chip is fabricated in a 0.25-μm standard CMOS process and the active area of DLL is 0.32×0.22mm2 and the loop filter consumes ~50% of the total active area. This DLL can be operated correctly when the input clock frequency is changed from 32 to 320MHz, and can generate ten-phase clocks within a single cycle. The measured mean value of the static phase offset is 22ps at 50MHz and the static phase offset is equal to 9.9ps at 200MHz. When the input clock is 200MHz, the measured rms random jitter is 4.44ps and the peak-to-peak deterministic jitter is 15ps. In chapter 4, a high-speed and ultra-low-voltage divide-by-4/5 counter for frequency synthesizer is proposed. The dynamic floating input D-flip-flop and several logic gates are merged to reduce the effective capacitance of the internal and external nodes, and to increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-μm CMOS process and the chip area is 21×9μm2. When the supply voltage is 0.5V, the measured maximum operating frequency of the proposed counter (divide-by-4) can reach 600MHz with a power consumption of 8.35μW. The proposed counter has a smaller PDP than conventional counters at sub-1V supply voltage. In chapter 5, an ultra-low-voltage phase-locked loop with bulk-input VCO is presented. The proposed PLL uses bulk-input and forward-body-bias techniques to enable operation at supply voltages of down to 0.5V to circumvent the threshold voltage problem and successfully demonstrated in solar cell applications. A 0.5V PLL is fabricated in a 0.13-μm 1.2V N-well CMOS process and the active area is 0.04mm2. The total power consumption of the PLL is 1.25mW at an operating frequency of 550MHz with a single 0.5V multicrystalline solar cell (59mV peak-to-peak supply noise). The measured rms jitter and peak-to-peak jitter are 8.76ps and 67.27ps, respectively.
關鍵字(中)	★ 鎖相迴路 ★ 延遲鎖定迴路 ★ 時脈同步電路	關鍵字(英)	★ Clock Synchronization Circuit ★ Delay-Locked Loop ★ Phase-Locked Loop
論文目次	Table of Contents i List of Figures iii List of Tables vi Chapter 1 Introduction to Clock Synchronization Circuits 1 1. 1 Introduction 1 1. 2 Delay-Locked Loops 2 1.2.1 Phase Detector 3 1.2.2 Charge Pump/Loop Filter 5 1.2.3 Voltage-Controlled Delay Line 7 1.2.4 Stability Analysis of DLL 8 1.3 Phase-Locked Loops 12 1.3.1 Phase Frequency Detector 14 1.3.2 Voltage-Controlled Oscillator 16 1.3.3 Loop Filter 17 1.3.4 Frequency Divider 18 1.3.5 PLL Linear Model Analysis 19 1.4 Thesis Overview 20 Chapter 2 Fast-Lock Delay-Locked Loop with Coarse Tune Technique 22 2.1 Motivation 22 2.2 Design Considerations of the Fast-Lock DLL 23 2.3 Architecture of the Proposed DLL 26 2.3.1 Power-On Reset Circuit 28 2.3.2 Coarse Tune Circuit 33 2.3.3 Delay Cell 34 2.3.4 Phase Detector 37 2.3.5 Charge Pump and Loop Filter 38 2.4 Experiment Results 39 2.5 Summary 41 Chapter 3 Wide-Range Delay-Locked Loop with Frequency Range Selector 43 3.1 Motivation 43 3.2 Design Considerations of the Wide-Range Delay-Locked Loop 44 3.2.1 Harmonic Locking Problem 45 3.2.2 Stuck Locking Problem 46 3.3 Architecture of the Proposed DLL 48 3.3.1 Frequency Range Selector 49 3.3.2 Multi-Controlled Delay Cells 50 3.3.3 Coarse Tune Circuit 52 3.3.4 Digital-Controlled Charge Pump 53 3.3.5 Phase Detector 54 3.4 Experimental and Comparative Results 55 3.5 Summary 60 Chapter 4 High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer 61 4.1 Motivation 61 4.2 Frequency Synthesizers with Prescaler 62 4.3 Architecture of Divide-by-4/5 Counter 65 4.3.1 Previous Divide-by-4/5 Counters 65 4.3.2 Proposed Divide-by 4/5 Counter 68 4.4 Simulation and Experimental Results 72 4.5 Summary 76 Chapter 5 Ultra-Low-Voltage Phase-Locked Loop with Bulk-Input VCO 77 5.1 Motivation 77 5.2 Concept of Low-Voltage CMOS Design 78 5.2.1 The Bulk-Driven Technique 79 5.2.2 The Body-Biasing Technique 82 5.3 Architecture of the Proposed PLL 84 5.3.1 Bulk-Input VCO 85 5.3.2 Divider Circuit 86 5.3.3 Calibration Circuit 87 5.4 Simulation and Experimental Results 88 5.5 Summary 93 Chapter 6 Conclusion and Future Work 95 Bibliography 98
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指導教授	鄭國興(Kuo-Hsing Cheng)	審核日期	2008-7-1
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