具自我校正之高解析度抖動量測電路應用於高速串列傳輸系統

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姓名

張志宇(Chih-yu Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

具自我校正之高解析度抖動量測電路應用於高速串列傳輸系統
(On-Chip High Resolution Jitter Measurement Circuit with Self-Calibration Technique for High-Speed Serial Link)

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摘要(中)

在半導體製程技術不斷的演進之下，積體電路已朝單晶片化的系統整合方式發展，當系統整合於同一晶片上時，電路在時序上的掌握就變得相當重要，若時脈的抖動量過大或具相位偏移時，會造成系統在操作上的錯誤。因此在系統上便會選擇鎖相迴路來當作參考時脈來源，但就目前單晶片化的趨勢與操作速度的提升，要直接對鎖相迴路的輸出時脈信號抖動量進行量測已變成相當困難，此外利用外部儀器量測不僅需花費高額的成本，且儀器所引發的雜訊也使得測試結果受到影響，基於上述理由，內建自我測試電路便因此而產生。
本論文提出的「具自我校正之高解析度抖動量測電路應用於高速串列傳輸系統」以提高量測解析度、減少面積消耗、降低製程變異影響為設計目標。以往量測電路皆需要一組額外信號來當作參考信號源且有元件不匹配的問題，本論文利用自我取樣的方法搭配游標尺環形振盪器的作法來消除參考信號源與電路不匹配的問題，同時也能降低面積的消耗，此外為了能量測到在高速串列傳輸系統中時脈信號的微小抖動量，在電路中再加上時間放大電路來增加量測的精準度，然而製程變異也會對量測結果造成影響，因此電路中額外再加上第一級自動校正電路與第二級校正電路來補償製程變異的影響。
本次抖動量測電路是利用UMC90nm 1P9M製程來設計，可量測到3GHz的時脈抖動量，整體電路的解析度為2.0ps，功率消耗約為11.43mW。

摘要(英)

As the improvement of semiconductor technology, VLSI circuit has developed in a system on chip (SoC). When system integrated into a chip, the clock synchronous problem of SoC would become very important. If the clock jitter is excessive or phase deviation, the mistakes of system operation will be generated. In view of this problem, clock synchronization circuits such as PLLs and DLLs will be used the clock source. But on a tendency toward SoC system and high operating speed, it is difficult to measure the output clock jitter of the PLL circuit directly. In addition, using external measuring equipments not only need to take the high cost of equipment and noise caused by the test results also affected. For these reasons, the built-in self-test circuitry for clock jitter measurement can be produced.
This thesis on-chip high resolution jitter measurement circuit with self-calibration technique for high-speed serial link is proposed to improve the measurement resolution. It can reduce the measurement circuit area and reduce process variation effect. The conventional jitter measurement circuits need an additional signal as the reference source. In this thesis, the use of self-refereed method with vernier ring oscillator can eliminate the problems of the reference source. It also reduces the circuit mismatch and the chip area. In addition, in order to measure the tiny clock jitter in high-speed serial link, the proposed circuit uses the time amplifier circuit to increase the high accuracy. However, process variation will also influence the measure results. Therefore, the first auto-calibration and second calibration circuits are used to compensate the process variation.
This jitter measurement circuit is designed in UMC90nm 1P9M process. It can measure the 3GHz clock jitter. The resolution of the overall circuit is 2.0ps and power consumption is about 11.43mW.

關鍵字(中)

★ 時間放大電路
★ 抖動量測電路
★ 內建測試電路

關鍵字(英)

★ time amplifier
★ jitter measurement
★ BIST

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 x
第一章緒論 1
1.1 研究動機 1
1.2 論文架構 3
第二章抖動基本定義 4
2.1 時脈抖動的基本定義與分類 4
2.1.1. 週期性時脈抖動與應用 (Jper) 5
2.1.2. 週期對週期性時脈抖動與應用 (Jcc) 6
2.1.3. 長期性時脈抖動與應用 (Jlong) 7
2.2 時脈抖動的來源 8
2.2.1. 定量性抖動 8
2.2.2. 隨機性抖動 9
2.3 時脈抖動直方圖(Clock Jitter Histogram) 10
第三章時脈抖動量測方法介紹 12
3.1 Off-chip外部時脈抖動量測設備 12
3.2 On-chip內部時脈抖動量測方法 13
3.3 常見On-chip抖動時脈量測電路介紹 14
3.3.1. 時間數位轉換電路(TDC)與時間電壓轉換電路(TVC)[15] 14
3.3.2. 雙斜率量測法(Dual Slop Method)[16] 16
3.3.3. 脈衝縮減延遲量測法(Pulse-Shrinking Method)[17] 17
3.3.4. 延遲串列量測法(Delay Chain Method)[18] 18
3.3.5. 游標尺延遲線量測法(Vernier Delay Line Method)[19] 20
3.3.6. 游標尺環型振盪器量測法(Vernier Ring Oscillator Method)[20] ……………………………………………………………………...21
第四章改良式游標尺環形振盪器之抖動量測電路 23
4.1 自我取樣技巧 23
4.2 改良式時脈抖動量測電路流程 25
4.3 改良式內建時脈抖動量測電路架構圖與子電路操作 26
4.3.1. 自我取樣電路[23] 26
4.3.2. 時間放大電路[25] 28
4.3.3. 游標尺環形振盪量測電路 30
4.3.4. 切換式計數器電路 33
4.3.5. 校正電路 35
4.4 電路操作 40
4.4.1. 校正模式 40
4.4.2. 量測模式與規格訂定 44
第五章電路模擬與晶片量測結果 46
5.1 子電路模擬結果 47
5.1.1. 自我取樣電路 47
5.1.2. 時間放大電路 48
5.1.3. 游標尺環形振盪電路 49
5.1.4. 切換式計數器電路 50
5.1.5. 校正電路 52
5.2 全電路模擬 53
5.2.1. 校正模式模擬 53
5.2.2. 量測模式模擬 59
5.3 電路佈局與晶片照像圖 61
5.3.1. 電路佈局 61
5.3.2. 晶片照相圖 63
5.4 晶片環境設定與量測結果 64
5.4.1. 環境設定 64
5.4.2. 量測結果 65
5.5 電路模擬與晶片量測結果比較 68
第六章結論與未來改進方向 69
6.1 結論 69
6.2 未來改進方向 69
Reference 71

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指導教授

鄭國興(Kuo-hsing Cheng)

審核日期

2008-11-14

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