兼併切換式電容及切換式放大器且應用於生醫訊號之三角積分調變器

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姓名

林妤穎(Yu-ying Lin) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

兼併切換式電容及切換式放大器且應用於生醫訊號之三角積分調變器
(A Sigma-Delta modulator for Bio-signals Measurement System Combining Switched-Capacitor and Switched-OPAMP Technique)

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摘要(中)

近年來，憑藉著醫學與超大型積體電路的演進，常見的生理訊號量測儀器已朝向多功能、可攜式與高精準度發展。在量測系統中，除低雜訊生醫放大器外仍需一高精密度之類比數位轉換器將訊號正確地交由數位訊號處理模組進行資料處理與分析。因此，本論文中選擇三角積分調變器 (SDM) 之類比數位轉換器，其可降低前端類比濾波器設計之困難與功率消耗，進而減少整體量測系統面積。
三角積分類比數位轉換器主要由三角積分調變器與數位降頻濾波器所組成。本文所設計之電路結合SC-SDM與SO-SDM之優點並將其整合，以低功率與高解析度為其設計標的完成一應用於所有生理訊號量測之三角積分調變器。電路實現上，在訊號頻寬10KHz、128倍超取樣率與±0.1V的輸入振幅下，所設計之二階三角積分調變器訊號雜訊失真比為70.5dB，有效位元數達到11.7位元且整體晶片消耗之功率為161μW。製作過程使用台積電0.18μm CMOS 1P6M製程，其晶片面積約佔1.035mm2。最後的量測結果顯示訊號雜訊失真比為46.2dB，有效位元數為7.7位元。在1.8V電源供應下，整體晶片消耗之功率約224μW。

摘要(英)

In recent years, public bio-signal measurement systems have been developed toward high accuracy, multi-functionality and portability due to the advancement of the medical science and VLSI technology. In addition to the bio-signal analog-front-end (AFE) circuits, measurement systems require a precision analog-to-digital (A/D) converter that can convert signals precisely to digital signal processing for analyzing data. Therefore, we choose the A/D converter which include Sigma-Delta modulator (SDM) to reduce anti-aliasing filter complexity and power consumption, resulting in reducing overall chip area of measurement systems.
A Sigma-Delta A/D converter mainly consists of SDM and decimation filter. In this thesis, the proposed SDM combines the advantages of Switched-Capacitor SDM (SC-SDM) and Switched-OPAMP SDM (SO-SDM). The SDM aiming at low power consumption and high resolution is accomplished for all applications of bio-signal measurement. The modulator achieves 70.5dB signal-to-noise and distortion ratio (SNDR), 11.7 effective number of bits (ENOB) , and power consumption 161μW at 10-KHz signal bandwidth with an oversampling ratio (OSR) of 128, and 0.2Vp-p amplitude. The circuit is fabricated in the TSMC 0.18-μm one-poly six-metals CMOS process, and chip area is 1.035mm2. Finally, the measurement results show that signal to noise distortion ratio is 46.2dB, and 7.7 effective number of bits. The measured power consumption is about 224μW for 1.8V power supply.

關鍵字(中)

★ 切換式電容
★ 切換式運算放大器

關鍵字(英)

★ switched-opamp
★ switched-capacitor

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 4
第二章三角積分調變器原理介紹 5
2.1 奈奎斯特與超取樣類比數位轉換器 5
2.2 量化誤差 7
2.3 超取樣與雜訊移頻技術 9
2.3.1 超取樣技術 9
2.3.2 雜訊移頻技術 10
2.4 超取樣三角積分調變器 12
2.4.1 一階三角積分調變器 12
2.4.2 二階三角積分調變器 14
2.5 高階三角積分調變器 15
2.5.1 單迴路三角積分調變器 17
2.5.2 串接式高階三角積分調變器 17
第三章切換式電容與切換式運算放大器之簡介 20
3.1 切換式電容積分器與切換式運算放大器積分器簡介 20
3.1.1 切換式電容積分器 20
3.1.2 切換式運算放大器積分器 23
3.2 二階切換式電容與切換式運算放大器之三角積分調變器系統簡介 25
3.2.1 二階切換式電容三角積分調變器 25
3.2.2 二階切換式運算放大器三角積分調變器 26
3.3 系統架構考量 29
第四章三角積分調變器設計與模擬 32
4.1 電路系統非理想效應考量 32
4.1.1 熱雜訊 32
4.1.2 取樣雜訊 34
4.1.3 運算放大器之非理想效應 40
4.2 規格制定 42
4.3 系統設計 43
4.4 電路設計 45
4.4.1 運算轉導放大器 45
4.4.1 量化器與一位元數位類比轉換器 49
4.4.2 非重疊時脈產生電路 50
4.5 系統模擬結果 52
第五章佈局與量測考量 56
5.1 佈局考量 56
5.2 量測考量 57
5.3 量測結果 59
第六章結論與未來展望 62
6.1 結論 62
6.2 未來展望 63
參考文獻 64

參考文獻

[1]J. G. Webster, “Medical Instrumentation Application and Design,” Canada: John Wiley & Sons., 1998
[2]C. M. Hsu, T. C. Yo and C. H. Luo, “An Ultra-Low Power Variable-Resolution Sigma-Delta Modulator for Signals Acquisition of Biomedical Instrument,” IEICE Transactions on Electronics, vol. E90-C, no. 9, pp. 1823-1829, Sep. 2007
[3]S. R. Norsworthy, R. Schreier and G. Temes, “Delta-Sigma Data Converters –Theory, Design, and Simulation,” New York: IEEE Press, 1997
[4]R. J. Baker, “CMOS-Circuit Design, Layout and Simulation,” Canada: John Wiley & Sons. , Second Edition, 2008
[5]D. Johns and K. Martin, “Analog Integrated Circuit Design,” New York: John Wiley & Sons. , 1997
[6]T. K. Wu and C. H. Luo, “The Implementation of Low Power Variable Resolution Sigma-Delta Modulator for Biomedical Applications,” National Cheng Kung University, Jun. 2006
[7]C.H. Su, “Circuit Implementation of Sigma-Delta Modulators,” Electrical Engineering, National Central University, 2007
[8]R. Schreier and G. C. Temes, “Understanding Delta-Sigma Data Converters,” Canada: John Wiley & Sons. , 2005
[9]R. J. Baker, “CMOS–Mixed Signal Circuit Design,” America: John Wiley & Sons. , 2002
[10]L. Yao, M. S. J. Steyaert and W. Sansen, “A 1-V 140-μw 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, no. 11, Nov. 2004
[11]K. C. H. Chao, S. Nadeem, W. L. Lee and C. G. Sodini, “A High Order Topology for Interpolative Modulators for Oversampling A/D Converters,” IEEE Transactions on Circuits and Systems, vol. 37, pp. 309-318, Mar. 1990
[12]A. Marques, “High Speed CMOS Data Converters,” Ph. D. thesis, ESAT-MICAS, K. U. Leuven, Belgium, 1999
[13]Y. Matsuya, A. Iwata and M. Ishikawa, “A 16-bit Oversampling A-to-D Conversion Technology using Triple-Integration Noise Shaping,” IEEE Journal of Solid-State Circuits, vol. 22, no. 6, pp. 921-929, Dec. 1987
[14]D. B. Ribner, “A Comparison of Modulator Networks for High-Order Oversampled ΣΔ Analog-to-Digital Converters,” IEEE Transactions on Circuits and Systems, vol. 38, no. 2, pp. 145-159, Feb. 1991
[15]L. R. Carley, “A Noise-Shaping Coder Topology for 15+ bit Converters,” IEEE Journal of Solid-State Circuits, vol. 24, no. 2, pp. 267-273, Apr. 1989
[16]P. E. Allen and D. R. Holberg, “CMOS Analog Circuit Design,” Oxford University Press, Jan. 2002
[17]A. M. Abo and P. R. Gray, “A 1.5-V 10bit, 14.3-Ms/s CMOS Pipeline Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999
[18]S. Y. Lee, “Analog Integrated Circuits,” Electrical Engineering, National Chung Cheng University, 2007
[19]V. S. L. Cheung and H. C. Luong, “Design of Low-Voltage CMOS Switched-Opamp Switched-Capacitor systems,” Boston: Kluwer Academic, Second Edition, 2003
[20]C. H. Kuo, “The Design and Implementation of Low Voltage CMOS Delta Sigma Modulators,” National Taiwan University, Jun. 2002
[21]P. C. Davis, S. F. Moyer and Veikko R. Saari, “Relationship Between Frequency Response and Settling Time of Operational Amplifiers,” IEEE Journal of Solid-State Circuits, vol. sc-9, no. 6, Dec. 1974
[22]J. Sauerbrey, T. Tille D. Schmitt-Landsiedel and R. Thewes, “A 0.7-V MOSFET-Only Switched-Opamp ΣΔ Modulator in Standard Digital CMOS Technology,” IEEE Journal of Solid-State Circuits, vol. 37, no. 12, Dec. 2002
[23]J. Crols and M. Steyart, “Switched-Opamp: An Approach to Realize Full CMOS Switched-Capacitor Circuits at Very Low Power Supply Voltages,” IEEE Journal of Solid-State Circuits, vol. sc-29, no. 8, pp. 936-42, Aug. 1994.
[24]V. Peluso, P. Vancorenland, M. Steyaert and W. Sansen, “A 900-mV Differential Class AB OTA for Switched-Opamp Applications,” Electronic Letters, vol. 33, no. 17, pp. 1455–6, Aug. 1997
[25]A. Baschirotto and R. Castello, “A 1-V 1.8MHz CMOS Switched-Opamp SC Filter with Rail-to-Rail Output Swing,” International Solid-State Circuits Conference, vol. sc-32, no. 12, pp. 1979-86, Dec. 1997.
[26]B. Razavi, “Design of Analog CMOS Integrated Circuits,” Mcgraw-Hill, Second Edition, 2005
[27]P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, “ Analysis and Design of Analog Integrated Circuits,” New York: John Wiley & Sons., Second Edition, 2001
[28]M. Gustavsson, J. J. Wikner and N. N. Tan, “CMOS Data Converters for Communications,” New York: Kluwer Academic Publishers, 2002
[29]H. C. Yang and D. J. Allstot, “Considerations for Fast Settling Operational Amplifiers,” IEEE Transactions on Circuits and Systems, vol. 37, no. 3, Mar. 1990
[30]P. Malcovati, S. Brigati, F. Francesconi, F. Maloberti, P. Cusinato and A. Baschirotto, “Behavioral Modeling of Switched-Capacitor Sigma-Delta Modulators,” IEEE Transactions on Circuits and Systems I, vol. 50, no. 3, Mar. 2003
[31]Z. M. Lee, “MOS Sampling Circuits,” Electrical Engineering, National Central University, 2009
[32]S. Kim, J. Lee, S. Song, N. Cho and H. Yoo, “An Energy-Efficient Analog Front-End Circuit for a Sub-1-V Digital Hearing Aid Chip,” IEEE Journal of Solid-State Circuits, vol. 41, no.4, Apr. 2006
[33]L. Yao, M. Steyaert and W. Sansen, “Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS,” Netherland: Springer, 2006
[34]A. Liu and H. Yang, “Low Voltage Low Power Class-AB OTA with Negative Resistance Load,” International Conference on Communications, Circuits and Systems Proceedings, vol. 4, pp. 2251-2254, Jun. 2006.
[35]A. Yukawa, “A CMOS 8-bit high speed A/D converter IC,” IEEE Journal of Solid-State Circuits, vol. sc-20, pp. 954-961, Dec. 1987
[36]J. Wu, “High-Speed Analog-to-Digital Conversion in CMOS VLSI,” Ph. D. Disseration, Stanford University, Mar. 1988
[37]H. Y. Lee, C. M. Hsu, S. C. Huang, Y. W. Shih and C.-H. Luo, “Designing Low power of Sigma Delta Modulator for Biomedical Application,” Biomedical Engineering Applications, Basis & Communications, no. 18, pp. 181–185, Aug. 2005.
[38]H. Y. Yang and R. Sarpeshkar, “A Bio-Inspired Ultra-Energy-Efficient Analog-to- Digital Converter for Biomedical Applications,” IEEE Transactions on Circuits and Systems I , vol. 53, no. 11, pp. 2349–2356, Nov. 2006.
[39]S. Y. Lee and C. J. Cheng, “A Low-Voltage and Low-Power Adaptive Switched- Current Sigma–Delta ADC for Bio-Acquisition Microsystems,” IEEE Transactions on Circuits and Systems I, vol. 53, no. 12, pp.2628–2636, Dec. 2006
[40]H. L. Chen, P. S. Chen and J. S. Chiang, “A Low-Offset Low-Noise Sigma-Delta Modulator with Pseudo Random Chopper-Stabilization Technique,” IEEE Transactions on Circuits and Systems I, vol. 56, no. 12, Dec. 2009

指導教授

薛木添(Muh-tian Shiue)

審核日期

2010-10-22

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