應用於次世代被動光纖網路傳輸之高速正交分頻多工傳收器設計

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：45

、訪客IP：3.22.42.189

姓名

張智翔(Chih-Hsiang Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於次世代被動光纖網路傳輸之高速正交分頻多工傳收器設計
(High Speed OFDM Transceiver Design for Next Generation PON Communication)

相關論文

★ 應用於2.5G/5GBASE-T乙太網路傳收機之高成本效益迴音消除器	★ 應用於IEEE 802.3bp車用乙太網路之硬決定與軟決定里德所羅門解碼器架構與電路設計
★ 適用於 10GBASE-T 及 IEEE 802.3bz 之高速低密度同位元檢查碼解碼器設計與實現	★ 基於蛙跳演算法及穩定性準則之高成本效益迴音消除器設計
★ 運用改良型混合蛙跳演算法設計之近端串音干擾消除器	★ 運用改良粒子群最佳化演算法之近端串擾消除器電路設計
★ 應用於多兆元網速乙太網路接收機類比迴音消除器之最小均方演算法電路設計	★ 光耦合隔離系統之接收端晶片電路設計與實現
★ 應用於光耦合隔離系統之發送端雜訊整形類比轉數位轉換器	★ 應用於數位視頻廣播系統之頻率合成器及3.1Ghz寬頻壓控震盪器
★ 地面數位電視廣播基頻接收器之載波同步設計	★ 適用於通訊系統之參數化數位訊號處理器核心
★ 以正交分頻多工系統之同步的高效能內插法技術	★ 正交分頻多工通訊中之盲目頻域等化器
★ 兆元位元率之平行化可適性決策回饋等化器設計與實作	★ 應用於數位視頻廣播系統中之自動增益放大器及接受端濾波器設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

光纖網路傳輸擁有高速、長距離的優勢使得發展10Gbps的次世代被動光纖網路 (Next Generation-Passive Optical Network) 為必然趨勢，在此高速傳輸下衍生出成本過高、實現困難的問題，因此將OFDM技術應用在光纖系統之研究為近年來熱門的討論主題。
在本論文中，基於應用在光纖系統的OFDM架構，我們將提出可以使用任意子載波來偵測同步非理想效應之架構，以提高有限頻帶中能使用的頻寬，並且提出一個結合取樣時脈同步與等化器，因而系統不需要多做同步電路，並使此架構可適用在10 Gbps PON系統中。
而在此高速應用中，所設計的電路能否達到光纖系統的高速需求與低成本最為重要，因此在硬體考量方面，本論文實現系統中的關鍵電路，高速FHT硬體，並應用於高速光纖OFDM系統中。電路設計使用90nm製程，核心面積為0.476x0.451 mm2為，核心時脈312.5MHz，在1.0V的電壓下，晶片功率為27.00mW。

摘要(英)

The advantages of optical fiber communications are high speed and long distance as a result of low transmission loss. To develop the Next Generation Passive Optical Network (NG-PON) is one of the main focuses. Particularly, the key issue is the cost-efficient device been feasible. Thus, OFDM technique in optical communication to increase spectral efficiency becomes popular in this domain.
In the thesis, we propose a new architecture for 10Gbps PON to detect the sampling clock offset using any subcarrier in each OFDM symbol. The proposed architecture joins timing recovery synchronization and equalization to reduce the cost of conventional timing synchronization for cost-efficiency and achieve a superior performance.
In hardware implementation, we propose the high speed FHT hardware to achieve high-speed circuit requirement in optical fiber communications. Whole circuit, designed in 90 nm CMOS process, occupied 0.476x0.451 mm2 of core area, and totally consumes 27.00 mW in 1.0 Volt supply voltage at the clock rate of 312.5 MHz.

關鍵字(中)

★ 被動光纖網路傳輸
★ 正交分頻多工

關鍵字(英)

★ PON
★ OFDM

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 viii
第一章緒論 1
1.1 研究動機 1
1.2 正交分頻多工 (OFDM) 調變簡介 2
1.2.1 OFDM 之數學模型 3
1.2.2 保護區間與循環前置碼 4
1.3 NG-PON 系統架構 5
1.4 論文架構 7
第二章 NG-PON 同步與等化架構設計 8
2.1 符碼邊界同步 8
2.1.1 符碼邊界偏移效應 8
2.1.2 符碼邊界偏移估測 10
2.2 取樣時脈同步 11
2.2.1 取樣時脈偏移效應 11
2.2.2 取樣時脈偏移估測 13
2.3 LMS頻域等化器 15
2.3.1 直角座標系 LMS 頻率等化器 16
2.3.2 極座標系LMS頻率等化器 17
2.4 結合時脈同步與頻域等化器架構設計 19
2.4.1 自動增益控制與載波回復的頻域等化器 19
2.4.2 取樣時脈回復等化器 22
2.4.3 結合取樣時脈同步與等化雙迴路架構 24
第三章 NG-PON系統模擬與結果 26
3.1 傳送與接收端系統架構建置 26
3.2 傳送與接收端系統模擬環境 28
3.3 模擬取樣時脈偏移與補償效應 30
3.4 星座圖模擬結果 32
3.5 系統效能模擬 34
第四章 NG-PON高速FHT架構設計 36
4.1 FHT / FFT 36
4.2 FHT演算法 37
4.2.1 Radix-2 DIF FHT演算法 37
4.2.2 Radix-4 DIF FHT演算法 40
4.2.3 Radix-8 DIF FHT演算法 44
4.3 DHT與DFT轉換公式 47
4.4 FHT/FFT演算法比較 48
4.5 高速FHT硬體設計 49
4.5.1 FHT設計規格 49
4.5.2 FHT演算法硬體特性 50
4.5.3 FHT硬體架構 51
第五章關鍵電路FHT晶片實作與量測結果 55
5.1 晶片設計流程 55
5.2 定點數分析 56
5.3 晶片設計 57
5.4 晶片規格 58
5.5 晶片量測 60
5.6 硬體比較 62
第六章結論與未來展望 64
參考文獻 65

參考文獻

[1] C. H. Lee, W. V. Sorin, B. Y. Kim, “Fiber to the Home Using a PON Infrastructure”, Journal of lightwave technology, vol . 24, no. 12, Dec. 2006.
[2] M. Hajduczenia, H. J. A. da Silva, “Next Generation PON Systems – Current Status”, in Proc. ICTON, pp.1-8, Jun. 2009.
[3] M. Engels, Wireless OFDM Systems, Kluwer Academic publishers, Jan. 2002
[4] D. Matiæ, “OFDM as a possible modulation technique for multimedia applications in the range of mm waves,” TUD-TVS, Oct. 1998
[5] Peled and A. Ruiz, “Frequency Domain Data Transmission using Reduced Computational Complexity Algorithms,” in Proc. IEEE International Conference on ICASSP, vol. 5, April, 1980, pp. 964-967
[6] J. J. van de Beek, M. Sandell and P. O. Borjesson, “ML Estimation of Time and Frequency Offset in OFDM Systems”, IEEE Transactions on singnal processing, vol. 45, no. 7, July 1997.
[7] P. H. Moose, ”A Technique for Orthogonal Frequency Division Multiplexing Frequency Offset Correction”, IEEE Transaction on communications, vol. 42, no. 10, October 1994
[8] M. Speth, S. A. Fechtel, G. Fock, and H. Meyr, “Optimum Receiver Design for Wireless Broad-Band Systems Using OFDM - Part I,” IEEE Transactions on Communications, vol. 47, no. 11, November 1999
[9] T. Pollet, M. Peeters and Alcatel, “Synchronization with DMT Modulation”, IEEE Communications Magazine, vol. 37, April 1999.
[10] M. Speth, S. A. Fechtel, G. Fock, and H. Meyr, “Optimum Receiver Design for Wireless Broadband Transmission – Part II: A Case Study,” IEEE Transactions on Communications, vol. 49, no. 4, April 2001
[11] S. Haykin, Adaptive Filter Theory, fourth ed., Prentice Hall, New Jersey, 2002
[12] M. T. Shiue and S. S. Long, “A Blind Frequency-Domain Equalization Algorithm for OFDM/DMT Systems Based on AGC and Carrier Recovery”, ITC-CSCC, July 2005.
[13] S. Moridi and H. Sari, “Analysis of Four Decision-Feedback Carrier Recovery Loops in The Presence of Intersymbol interference,” IEEE Transactions of Wireless Communications, vol. COM-33, 1985, pp. 543-550
[14] C. F. Wu, M. T. Shiue and C. K. Wang, “Joint Carrier Synchronization and Equalization for Packet-Based OFDM Systems in Multipath Fading Channel”, IEEE Transactions on Vehicular Technology. April 2009. pp1-5.
[15] R. E. Best, Phase-Locked Loops, third ed., McGraw-Hill, 1997
[16] F. M. Gardner, Phaselock Techniques, third ed., Wiley, New Jersey, 2005
[17] Y. M. Lin, “The Channel Equalizer for High Speed Optical Fiber Communications”, CCL Technical Journal, Sep. 2005.
[18] R. N. Bracewell, “Discrete Hartley Transform”, J. Opt. Soc. Amer., Vol. 73, pp. 1832-1835,1983.
[19] R. N. Bracewell, “The Fast Hartley Transform”, Proceedings of the IEEE, vol. 72, no. 8, pp. 1010-1018, Aug. 1984.
[20] C. L. Wang and C. H. Chang, “A Novel DHT-based FFT/IFFT Processor for ADSL Transceivers”, Circuits and Systems, ISCAS`99, Vol. 1, pp. 51–54, Jun. 1999.
[21] C. L. Wang and C. H. Chang, “A DHT-based FFT/IFFT Processor for VDSL Transceivers”, IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 2, pp. 1213-1216, May 2001.
[22] T. C. Pao, C. C. Chang and C. K. Wang, ”A Variable-Length DHT-based FFT/IFFT Processor For VDSL/ADSL Systems”, IEEE Asia-Pacific Conference on Circuits and Systems, Vol. 1, pp. 381-384, Dec. 2004.
[23] A. C. Erickson and B. S. Fagin, “Calculating the FHT in Hardware”, IEEE Trans. on Signal Processing, Vol. 40 No. 6, pp. 1341-1353, Jun. 1992.
[24] J. I. Guo, “An Efficient Design for One-Dimensional Discrete Hartley Transform Using Parallel Additions”, IEEE Trans. on Signal Processing, Vol. 48, No. 10, pp. 2806-2813, Oct. 2000.
[25] H. C. Chen, T. S. Chang, J. I. Guo, C. W. Jen, “The Long Length DHT Design With a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning”, IEICE Trans. Electron., Vol. E88-C,No. 5, pp. 1061-1069, May 2005.
[26] T. C. Pao, “Design of a Variable-Length DHT-Based FFT Processor for VDSL, “Master Thesis, Institute of Electronics Engineering, National Taiwan University, Taipei City, Taiwan, Jul. 2003.
[27] C. R. Johnson and W. A. Sethares, Telecommunication Breakdown, Pearson Prentice Hall, Upper Saddle River, New Jersey, 2004.
[28] K. Maharatna, E. Grass, and U. Jagdhold, “A 64-Point Fourier Transform Chip for High-Speed Wireless LAN Application using OFDM”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 3, pp. 484-493, Mar. 2004.
[29] C. T. Lin, Y. C. Yu, and L. D. Van, “A Low-Power 64-Point FFT/IFFT Design for IEEE 802.11a WLAN Application”, IEEE International Symposium on Circuit and System, pp. 4523-4526, May 2006.
[30] W. C. Yeh and C. W. Jen, “High-Speed and Low-Power Split-Radix FFT,” IEEE Trans. on signal processing, Vol. 51, No. 3, March, 2003
[31] C. F. Wu, M. T. Shiue and C. K. Wang, “Joint Carrier Synchronizationand Equalization for OFDM Systems over Multipath Fading Channel,” IEEE 68th Vehicular Technology Conf., Sept. 2008, pp. 1-5.
[32] B. M. Baas, “A Low-Power, High-Performance, 1024-Point FFT Processor,” IEEE J. Solid-State Circuits, vol. 34, pp. 380-387, Mar. 1999.
[33] Y. Chen, Y. W. Lin, Y. C. Tsao, C. Y. Lee, “A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems,” IEEE J. Solid-State Circuits, vol. 43, pp. 1260-1273, May 2008.

指導教授

薛木添(Muh-Tian Shiue)

審核日期

2009-11-14

推文