操作於1伏特以下及具固定電壓控制震盪器增益值之鎖相迴路

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姓名

邱昭彰(Chao-Chang Chiu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

操作於1伏特以下及具固定電壓控制震盪器增益值之鎖相迴路
(A Sub-1V Phase-Locked Loop with Constant KVCO Technique)

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摘要(中)

節能減碳為近年來電路設計上越來越受到重視的議題，鎖相迴路是通訊系統中用來產生同步時脈的重要電路，因此也不能忽略鎖相迴路的功率消耗。降低功率消耗的方法中，最直接的做法就是降低操作電壓；在本論文中提出一個可操作在0.9-V，並輸出1.25-GHz 八個相位的鎖相迴路，以達到高操作頻低功率消耗的目的。
但在低電壓的鎖相迴路設計中存在著許多設計上的困難，包括漏電流問題、避免電晶體疊接和過大的臨界電壓值等，如何正確且穩定的操作在低電壓下將在本論文中詳細探討。論文中提出一個具閘級回授充電幫浦，可有效降低充放電之電流不匹配問題，以達到降低壓控震盪器控制電壓之抖動，進而提升鎖相迴路的性能。此外，在寬頻率範圍的多頻帶壓控震盪器設計中，無論是LC震盪器，亦或是環型震盪器往往會存在KVCO (頻率對電壓變化之斜率) 變化劇烈的問題，這將會衍生出許多的問題。因此在本論文亦提出了一個可在製程、電壓、溫度變異下均能避免此問題之全新固定電壓控制震盪器增益值技術。
本晶片採用TSMC 0.18 UM CMOS Mixed Signal RF General Purpose MiM Al 1P6M 1.8&3.3V製程實現，當輸出為1.25GHz時，功率消耗為3.7mW，其輸出的抖動
為6 ps (p-p)，晶片的核心部分面積為0.09 mm2。

摘要(英)

The issue of energy saving and carbon reduction is more and more important on circuit design. Phase-locked loop (PLL) is one of the important blocks in communication system. Thus, the power consumption of PLL is not able to ignore. To reduce supply voltage is the easiest way to decrease power consumption. A 0.9-V 1.25 GHz 8-phase PLL is proposed to achieve high output frequency and low power consumption.
There are several problems in the low voltage PLL design, inculding leakage current, MOSFET cascade and threshold voltage ,etc. We will discuss about how to operate correctly and stably in low supply voltage. This PLL uses a gate-feedback technique to reduce the current mismatch problem of the charge pump. Therefore, the output frequency jitter will be decreased and the performance of PLL will be improved. In addition, both LC oscillator and ring oscillator have the dramatic variation of KVCO in the wide range multi-band voltage control oscillator design. A novel constant-KVCO technique was proposed to avoid the problem with the process, voltage, and temperature variations.
This chip is implemented in TSMC 0.18 UM CMOS Mixed Signal RF General Purpose MiM Al 1P6M 1.8&3.3V process. The output jitter performance of the proposed PLL is 2.79 ps (peak-peak) at 1.25- GHz. The power consumption of the PLL is 3.7 mW at 1.25-GHz and the core area is 0.09 mm2

關鍵字(中)

★ 低電壓
★ 鎖相迴路

關鍵字(英)

★ low voltage
★ pll
★ phase-locked loop

論文目次

第1章緒論1
1.1動機1
1.2低電壓鎖相迴路挑戰1
1.3論文組織.2
第2章鎖相迴路基本觀念.3
2.1 鎖相迴路操作原理及組成元件3
2.1.1相位頻率偵測器.5
2.1.2充放電幫浦9
2.1.3迴路濾波器..12
2.1.4電壓控制震盪器..13
2.1.5除頻器.17
2.2鎖相迴路的系統分析.18
2.2.1公式推導...18
2.2.2Matlab模擬.24
第3章多頻帶壓控震盪器之分析比較..27
3.1常用的多頻帶壓控震盪器.29
3.1.1 電流切換式多頻帶壓控震盪器29
3.1.2 電容切換式多頻帶壓控震盪器31
3.2壓控震盪器頻帶數最佳化.32
第4章低操作電壓多頻帶鎖相迴路設計與製作.36
4.1 低操作電壓之電路設計技巧..37
4.2 低操作電壓鎖相迴路的組成與元件.39
4.2.1 相位頻率偵測器.39
4.2.2 充放電幫浦43
4.2.3 迴路濾波器49
4.2.4 具固定電壓控制震盪器增益值之多頻帶電壓控制震盪器..50
4.2.5 除頻器.59
4.3 低操作電壓鎖相迴路模擬結果61
第5章晶片佈局及量測65
5.1鎖相迴路電路佈局.65
5.2 晶片量測考量.68
第6 章結論70
參考文獻71

參考文獻

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指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2010-7-30

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