三維積體電路的微凸塊分配與晶粒間繞線之研究

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姓名

張佳仁(Chia-Jen Chang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

三維積體電路的微凸塊分配與晶粒間繞線之研究
(Micro-Bump Assignment and Inter-Die Routing for 3D ICs)

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摘要(中)

在現代積體電路設計中，隨著製程技術的進步，同一塊晶片中可以容納的元件數目愈來愈多，種類愈趨多樣化，晶片的面積也愈來愈小。在效能的部份，整體線長對效能的影響很大，較短的線長可以給系統帶來較佳的延遲時間，同時功率的消耗也會比較小。綜合以上的優點，三維積體電路(3D IC)的架構被提出來，對於同樣效能的製程而言，三維積體電路具有較低的技術成本，是目前很熱門的技術。
在這個研究中，運用了整數線性規畫(Integer Linear Programming)的方法，使用兩個階段的微凸塊(micro bump)訊號配置(signal assignment)，以及不規則陣列的重新分配層(redistributed layer, RDL)繞線，針對分布於三維積體電路內，做層與層之間接點的繞線。首先，在繞線框內已被預先定義的陣列中，選擇不會造成繞線交越(crossing)的微凸塊，接下來電路繞線就被分為上下兩層，分別為上重新分配層(upper RDL)及下重新分配層(lower RDL)。以最短線長和沒有交越的情況為目標，分別對這兩層需要被連接的點做繞線，求出最理想的全域繞線(global routing)解。實驗結果顯示，在合理的執行時間內，我們的方法可以達到100%的可繞線度，同時也能得到理想的總線長。

摘要(英)

The three dimensional integrated circuit (3D IC) is an emerging technology. It has a great potential on alleviating the long interconnect problems and integrating heterogeneous components for System-on-Chip (SoC) or System-in-Package (SiP) by stacking multiple active layers together. The primary emphasis on 3D-IC routing is the interface issues across dies. To handle the interface issue of connections, the inter-die routing, which uses micro bumps and two RDLs (Re-Distribution Layers) to achieve the connection between adjacent dies, is adopted.
In this thesis, we present an inter-die routing algorithm for 3D ICs with a pre-defined netlist. Our algorithm is based on integer linear programming (ILP) and adopts a two-stage technique of micro-bump assignment followed by irregular RDL routing. First, the micro-bump assignment selects suitable micro-bumps for the pre-defined netlist such that no crossing problem exists inside the bounding boxes of each net. After the micro-bump assignment, the netlist is divided into two sub-netlists, one is for the upper RDL and the other is for the lower RDL. Second, the irregular RDL routing determines minimum and non-crossing global paths for sub-netlists of the upper and lower RDLs individually. Experimental results show that our approach can obtain optimal wirelength and achieve 100% routability under reasonable CPU times.

關鍵字(中)

★ 微凸塊分配
★ 三維積體電路
★ 繞線

關鍵字(英)

★ Routing
★ Micro-Bump Assignment
★ 3D ICs

論文目次

Abstract (Chinese) i
Abstract ii
Acknowledgement iii
Table of Contents iv
List of Tables vi
List of Figures vii
Chapter 1. Introduction 1
1.1 3D IC Technology ..................................................................................................... 1
1.1.1 Dies Stacking ……………………………………………………………… 2
1.1.2 Inter-strata Connection ……………………………………………………. 2
1.1.3 Interface Connection ……………………………………………………… 3
1.2 Problem Formulation ………………………………………………………………. 4
1.3 Our Contributions ………………………………………………………………….. 6
Chapter 2. Related Works 8
2.1 Redistributed Layer ………………………………………………………………… 8
2.2 Network-Flow-Based RDL Routing ……………………………………………….. 9
2.2.1 Basic Network Formulation ……………………………………………….. 12
2.2.2 Capacity Assignment and Node Construction …………………………….. 13
2.3 ILP-Based RDL Routing …………………………………………………………… 15
2.3.1 Integer Linear Programming ………………………………………………. 15
2.3.2 ILP Formulation …………………………………………………………… 16
2.4 Comparison Among Our And Related Works ……………………………………… 19
Chapter 3. Proposed Approach 21
3.1 Algorithm Overview ………………………………………………………………… 21
3.2 Micro-Bump Assignment …………………………………………………………… 22
3.3 Irregular RDL Routing ……………………………………………………………… 25
3.3.1 Routing Network Construction …………………………………………… 26
3.3.2 Basic ILP Formulation ……………………………………………………. 28
3.3.3 ILP Reduction …………………………………………………………….. 32
Chapter 4. Experimental Results 34
Chapter 5. Conclusions and Future Works 39
Bibliography 40

參考文獻

[1] http://lpsolve.sourceforge.net/5.5/.
[2] http://www.itri.org.tw.
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[4] C. Chiang and S. Sinha, “The Road to 3D EDA Tool Readiness,” in Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference, pp. 429--436, 2009.
[5] J. Cong, A. Jagannathan, Y. Ma, G. Reinman, J. Wei, and Y. Zhang, “An Automated Design Flow for 3D Microarchitecture Evaluation,” in Proceedings of ACM/IEEE Asia and South Pacific Design Automation Conference, pp. 384--389, 2006.
[6] S. Das, A. Chandrakasan, and R. Reif, “Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI, pp. 13--18, 2003.
[7] J.-W. Fang, I.-J. Lin, Y.-W. Chang, and J.-H. Wang, “A Network-Flow based RDL Routing Algorithm for Flip Chip Design,” in IEEE Transactions on Computer-Aided Design, Vol. 26, No. 8, pp. 1417--1429, August 2007.
[8] J.-W. Fang and Y.-W. Chang, “Area-I/O Flip-Chip Routing for Chip-Package Co-Design,” in Proceedings of IEEE/ACM International Conference on Computer Aided Design, pp. 518--522, 2008.
[9] J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, “An Integer Linear Programming based Routing Algorithm for Flip-Chip Designs,” in IEEE Transactions on Computer-Aided Design, Vol. 28, No. 1, pp. 98--110, January 2009.

指導教授

陳泰蓁、劉建男
(Tai-Chen Chen、Chien-Nan Liu)

審核日期

2009-7-15

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