參考文獻 |
[1] 唐經洲, “為何不用SoC?,” CTimes,零組件雜誌,四月號2009.
[2] 唐經洲, “3D IC有其他好處嗎?,” CTimes,零組件雜誌, 五月號, 2009.
[3] 張嘉華, 唐經洲, “3D IC應用市場核心技術TSV的概況與未來,” CTimes, 零組件雜誌, 九月號2009.
[4] 鈴木茂夫 著, 白中和 譯, “容易瞭解的高頻技術入門,” 建興文化事業有限公司 2007.
[5] 陳耿男, “匯流排上的時間延遲及交談失真的偵錯設計技巧,” 國立中央大學電機工程學系碩士論文 2006.
[6] “Market trends for 3D stacking,” Yole, Tech. Rep., 2008, http://www.emc3d.org/documents/library/marketAnalysis_3D/YOLE3D%20IC.pdf.
[7] J. Cho, J. Shim, E. Song, J.S. Pak, J. Lee, H. Lee, K. Park and J. Kim, “Active Circuit to Through Silicon Via (TSV) Noise Coupling,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems 2009, pp. 97-100, Oct. 2009.
[8] G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, “Electrical Modeling and Characterization of Through-Silicon Vias (TSVs) for 3-D Integrated Circuits,” IEEE Transactions on Electron Devices, pp. 256-262, Jan. 2010.
[9] R. Gharpurey, and R. G. Meyer, “Modeling and Analysis of Substrate Coupling in Integrated Circuits,” IEEE Journal of Solid-State Circuits, pp. 344-353, Mar. 1996.
[10] 游祥凱, “使用於矽穿孔耦合分析之垂直十字鏈基板結構,” 國立中央大學電機工程學系碩士論文 2010.
[11] R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, and L.R. Zheng, “Compact Modelling of Through-Silicon Vias (TSVs) in Three-Dimensional (3-D) Integrated Circuits,” IEEE International Conference on 3D System Integration 2009, pp. 1-8, Sep. 2009.
[12] N.H. Khan, S.M. Alam, and S. Hassoun, “Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs,” IEEE International Conference on 3D System Integration 2009, pp. 1-7, Sep. 2009.
[13] From:J. Cho; J. Kim; T. Song; J. S. Pak; J. Kim; H. Lee; J. Lee; K. Park, “Through silicon via (TSV) shielding structures Through,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems 2010, pp. 269 - 272 , Oct. 2010
[14] L. Hui Chen and M. Marek-Sadowska, “Aggressor Alignment for Worst-Case Crosstalk Noise,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 612–621, May 2001.
[15] J. Pak, C. Ryu, and J. Kim, “Electrical Characterization of Through Silicon Via (TSV) depending on Structural and Material Parameters based on 3D Full Wave Simulation,” International Conference on Electronic Materials and Packaging 2007, pp. 351-354, May 2008.
[16] S.W. Tu, Y.W. Chang, and J.Y. Jou, “RLC Coupling-Aware Simulation and On-Chip BUS Encoding for Delay Reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 2258-2264, Oct. 2006.
[17] C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim, “High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging,” Electronics System integration Technology Conference, pp.215-220, Sep. 2006.
[18] E. Salman, and E. G. Friedman, “Methodology for placing localized guard rings to reduce substrate noise in mixed-signal circuits,” Research in Microelectronics and Electronics 2008, pp. 85-88, Apr. 2008.
[19] J. S. Yang, and A.R. Neureuther, “Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner,” International Symposium on Quality Electronic Design 2008, pp. 352-356, Mar.2008.
[20] J. Kim, E. Song, J. Cho, J.S. Pak, J. Lee, H. Lee, K. Park, and J. Kim, “Through silicon via (TSV) equalizer,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems 2009, pp. 13-16, Oct. 2009.
[21] T. Bandyopadhyay, R. Chatterjee, C. Daehyun, M. Swaminathan, and R. Tummala, “Electrical modeling of Through Silicon and Package Vias,” IEEE International Conference on 3D System Integration 2009, pp. 1-8, Sep. 2009.
[22] P. Y. Wu, S.Y.S. Tsui, and P.K.T. Mok, “Area- and power-efficient monolithic buck converters with pseudo-type III compensation, ’’ IEEE J. Solid-State Circuits, vol.45, no.8, pp.1446-1455, Aug. 2010.
[23] [20] K. J. Chang, N. H. Chang, S. Y. Oh, and K. Lee, “Parameterized SPICE Subcircuits for Multilevel Interconnect Modeling and Simulation,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, pp. 779–789, Nov. 1992.
|