多孔矽薄膜轉移之研究

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：18

、訪客IP：18.117.8.41

姓名

陳凱傑(Kai-Jie Chen) 查詢紙本館藏

畢業系所

機械工程學系

論文名稱

多孔矽薄膜轉移之研究
(The study of porous silicon thin-film transfer)

相關論文

★ 塑膠機殼內部表面處理對電磁波干擾防護研究	★ 研磨頭氣壓分配在化學機械研磨晶圓膜厚移除製程上之影響
★ 利用光導效應改善非接觸式電容位移感測器測厚儀之研究	★ 石墨材料時變劣化微結構分析
★ 半導體黃光製程中六甲基二矽氮烷之數量對顯影後圖型之影響	★ 可程式控制器機構設計之流程研究
★ 伺服沖床運動曲線與金屬板材成型關聯性分析	★ 鋁合金7003與630不銹鋼異質金屬雷射銲接研究
★ 應用銲針尺寸與線徑之推算進行銲線製程第二銲點參數優化與統一之研究	★ 複合式類神經網路預測貨櫃船主機油耗
★ 熱力微照射製作絕緣層矽晶材料之研究	★ 微波活化對被植入於矽中之氫離子之研究
★ 矽/石英晶圓鍵合之研究	★ 奈米尺度薄膜轉移技術
★ 光能切離矽薄膜之研究	★ 氮矽基鍵合之研究

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 ( 永不開放)

摘要(中)

在半導體製程技術中，依循著摩耳定律（Moore，s Low）前進。隨著時代的發展，半導體產業製程技術已進入奈米製程。由於元件尺寸越做越小，在傳統矽塊材（Bulk Silicon）晶圓材料會衍生出許的問題，如：寄生效應、閉鎖效應、軟錯效應、基材漏電流與過熱…等問題，利用製作絕緣層矽晶（Silicon on insulator, SOI）材料結構可以解決以上這些問題。目前常見製作絕緣層矽晶材料的方法為Smart-Cut®製程，利用高劑量氫離子佈植於矽晶圓內，再經晶圓鍵合製程與高溫退火處理，使氫離子聚集產生裂縫剝離以達到薄膜轉移之目的。由於Smart-Cut®製程中離子佈植機設備高昂，使用高強度離子束容易損傷晶圓，且佈植深度難以超過一微米，故利用電化學蝕刻的方式，可以製作出厚層之薄膜轉移，又能大幅降低成本。
本研究之目的為使用電化學蝕刻的方式，依照不同蝕刻參數，以電化學蝕刻P型重掺雜矽晶圓，蝕刻出雙層多孔矽，再與已另一片生成二氧化矽之矽晶圓鍵合，利用高溫退火，製作出深埋破裂層與微米厚的多孔回復晶矽薄膜。多孔回復晶矽薄膜可沿著深埋破裂層施以應力而產生剝離，達到薄膜轉移之目的，所形成薄膜厚度約為3〜10微米，此方法結合晶圓鍵合可以製作厚膜絕緣層矽晶（SOI）材料。

摘要(英)

In the semiconductor manufacturing technology which follows the Moor’’s law in the past. The development of the semiconductor industry has entered the nanoscale processes. As the size of devices are manufactured to be much smaller, some problems come up with the use of traditional silicon bulk wafer material, such as the parasitic capacitance, latch-up, short channel effects, the substrate leakage current and overheating ,and so on. These problems can be solved by using silicon on insulator material structure. Smart-Cut® process is a common technology for manufacturing the SOI material. By implanting the high doses of hydrogen ion into the silicon wafer, wafer bonding process and annealing process, the hydrogen ions will accumulate and thus create cracks to finish thin film transfer. Due to expensive ions implantation equipment which is easy to cause damage because of high ion implanting doses into silicon wafer. It’s difficult to obtain over 1 micron of implanting depth. Thus, electrochemical etching method can achieve thicker film transfer and the price is cheaper.
The purpose of this study is to use electrochemical etching method, heavily doped P-type silicon wafer was electrochemically etched based on different etching parameters which forms a porous silicon (PS) bilayer. Then bonding porous silicon (PS) bilayer with a silicon specimen covered with thermal oxide layer. The porous silicon (PS) bilayer with a buried separation layer and recrystallization layer with a few microns thickness has been finished through high temperature annealing and can be split when a stress is applied on buried separation layer to achieve the film transfer, the transfered film thickness is about 3 to 10 microns which provides another process to fabricate SOI material.

關鍵字(中)

★ 多孔矽
★ 電化學蝕刻
★ 絕緣層矽晶
★ 晶圓鍵合
★ 薄膜轉移
★ 退火

關鍵字(英)

★ Silicon on insulator
★ Electrochemical etching
★ Porous Silicon
★ Wafer bonding
★ Annealing
★ Thin-film transfer

論文目次

中文摘要…………………………………………………………………i
英文摘要………………………………………………………………ii
誌謝……………………………………………………………………iii
目錄…………………………………………………………………….iv
圖目錄…………………………………………………………………vii
表目錄……………………………………………………………………x
第一章緒論…………………………………………………………1
1-1 研究背景………………………………………………………1
1-2 研究動機………………………………………………………4
第二章原理與文獻回顧……………………………………………9
2-1 形成多孔矽之基礎理論………………………………………9
2-1.1 多孔矽製作技術………………………………………10
2-1.2 多孔矽電化學蝕刻中的電流－電壓（I-V）特性……12
2-1.3 多孔矽的溶解化學反應………………………………14
2-1.4 多孔矽形成機制………………………………………16
2-1.4.1 貝爾模型………………………………………16
2-1.4.2 量子模型………………………………………17
2-1.4.3 擴散限制模型…………………………………17
2-1.5 多孔矽的高溫退火……………………………………18
2-2 晶圓鍵合技術………………………………………………19
2-2.1 鍵合技術簡介…………………………………………19
2-2.2 直接（無介質層）晶圓鍵合技術……………………20
2-2.2.1 直接鍵合………………………………………20
2-2.2.2 低溫鍵合………………………………………22
2-2.2.3 陽極鍵合………………………………………23
第三章實驗準備與步驟…………………………………………33
3-1 實驗試片與器材準備………………………………………33
3-2 實驗晶片清潔………………………………………………34
3-3 電化學蝕刻設備……………………………………………36
3-4 高溫退火設備………………………………………………37
3-5 分析儀器介紹………………………………………………38
第四章結果與討論………………………………………………42
4-1 雙重不同定電流參數電化學蝕刻雙層多孔矽結果與討論…42
4-2 雙層多孔矽高溫退火結構變化結果與討論………………45
4-3 薄膜轉移後結果與討論……………………………………49
第五章結論與未來展望…………………………………………67
5.1 結論…………………………………………………………67
5.2 未來展望……………………………………………………68
參考文獻……………………………………………………………….69

參考文獻

【1】 Scott E. Thompson and Srivatsan Parthasarathy, “Moore's law: the future of Si microelectronics”, Science, Vol. 9, Issue 6, pp.20-25, 2006.
【2】 G. K. Celler and S. Cristoloveanu, “Frontiers of Silicon-on- Insulator” , Journal of Applied Physics, Vol. 93, Issue 9, pp. 4955-4978, 2003.
【3】莊達人，VLSI 製造技術，五版，高立圖書有限公司，臺北縣，2004.
【4】陳威良，「電漿離子佈植製作SOI及佈植缺陷之研究」，國立清華大學，碩士論文，2003.
【5】 J. B. Kuo and K.-W. Su, CMOS VLSI Engineering：Silicon-on-Insulator（SOI）, Kluwer Academic Publishers, Boston, 1998.
【6】 J.-P. Colinge, “Silicon-on-Insulator Technology: Materials to VLSI, 3rd Edition”, Springer Science+Business Media, Inc., New York, 2004.
【7】 J. B. Lasky, et al., “Silicon-on-Insulator（SOI）by Bonding and Etch-Back”, Electron Devices Meeting, 1985 International, Vol. 31, pp.684-687, 1985.
【8】 Q, -Y. Tong and U. Gossel, “Semiconductor Wafer Bonding：Science and Technology”, John Wiley, New York, 1999.
【9】 M. Bruel, “Silicon on insulator material technology”. Electronics Letters,Vol. 31, Issue 14, pp. 1201-1202, Jul 1995.
【10】 M. Bruel, “Process for the production of thin semiconductor material films”, US Patent 5,374,56, Commissariat Al 'Energie Atomique, 1992.
【11】 T.-H. Lee, “Semiconductor thin film transfer by wafer bonding and advanced ion implantation layer splitting technologies”, Duke University,
Ph.D. Dissertation, 1998.
【12】 NC. Bartelt et al., “Ostwald ripening of two-dimensional islands on Si (001)”, Physical Review, B., Vol.54, pp.741-751, 1996 .70
【13】 T Yonehara et al., “ELTRAN® ；SOI Wafer Technology ELTRAN”, JSAP International, No.4, pp10-16, 2001.
【14】 A. Uhir, “Electrolytic shapping of germanium and silicon”, Bell System Tech. J., Vol. 35, pp. 333, 1956.
【15】 3T. Osaka, K. Ogasawara, and S. Nakahara, “Classification of the pore structure of n-type silicon and its microstructure”, J. Electrochem. Soc. 144, 3226, 1997.
【16】 C. L. Clement, A. Lagoubi, and M. Tomkiewicz, “Morphology of porous n-type silicon obtained by photoelectrochemical etching”, J. Electrochem. Soc. 141, 958, 1994.
【17】 C. Levy-Clement, A. Lagoubi, R. Tenne, and M. Neumann-Spallart, “Photoelectrochemical etching of silicon”, Electrochim. Acta 37(5), 877, 1992.
【18】 A. A. Yaron, S. Bastide, J. L. Maurice, and C. L. Clement, “Morphology of porous n-type silicon obtained by photoelectrochemical etching II”, J. Lumin. 57, 67, 1993.
【19】 X.G. Zhang, S.D. Collins, R.L. Smith, “Porous Silicon Formation and Electropolishing of Silicon by Anodic Polarization in HF Solution”, J. Electrochem. Soc., Vol. 136, Issue 5, pp. 1561-1565, 1989.
【20】 X.G. Zhang, “Mechanism of Pore Formation on n ‐ Type Silicon”, J.electrochem. Soc., Vol. 138, Issue 12, pp. 3750-3756, 1991.
【21】 V. Lehmann, “The Physics of Macropore Formation in Low Doped n-Type Silicon”, J.electrochem. Soc., Vol. 140, pp. 2836, 1993.
【22】 C. Pickering, M.J. Beale, D.J. Robbins, P.J. Pearson, and R. Greef, “Optical studies of the structure of porous silicon films formed in p-type degenerate and non-degenerate silicon”, J. Phys. C: Solid state Phys., Vol.717, pp. 5535, 1984.
【23】 M.J. Beale, J.D. Benjamin, M.J. Uren, N.G. Uren, N.G. Chew and A.G. Cullis, “An experimental and theoretical study of the formation and microstructure of porous silicon”, J. Cryst. Growth, Vol.73, pp. 622, 1985.
【24】 M.J. Beale, J.D. Benjamin, M.J. Uren, N.G. Uren, N.G. Chew, and A.G. Cullis, “Microstructure and formation mechanism of porous silicon”, Appl. Phys. Lett., Vol. 46, pp. 86, 1985.
【25】 I. M. Young, M. I. Beale and J.D. Benjamin, “X‐ray double crystal diffraction study of porous silicon”, Appl. Phys. Lett., Vol.46, pp. 1133,1985.
【26】 R.L. smith, S.D. Collins, “Porous silicon formation mechanism”, J. Appl. Phys., Vol. 71, R1, 1992.
【27】 V. Lehmann, H. Foll, “Formation mechanism and properties of electrochemically etched trenches in n-type silicon”, J. Electrochem. Soc., Vol. 137, pp. 653, 1990.
【28】 V. Lehmann, W. Honlein, R. Reisinger, A. Spitzer, H. Wendt, and J. Willer, “A novel capacitor technology based on porous silicon” Thin Solid Films, Vol. 276, pp. 138, 1996.
【29】 V. Lehmann, U. Gosele, “Porous silicon formation: A quantum wire effect”, Appl. Phys. Lett., Vol. 58, pp. 865, 1991.
【30】 V. Lehmann, “Porous silicon-a new material for MEMS”, Proc. MEMS’96, pp. 1-6 , 1996.
【31】 A.J. Read, R.J. Needs, K.J. Naish, L.T. Canham, P.D.J. Calcott, and A. Qteish, “First-principles calculations of the electronic properties of silicon
quantum wires”, Phys, Rev. Lett., Vol. 69, pp. 1232, 1992.
【32】 G. D. Sanders and Y. C. Chang, “Theory of optical properties of quantum 72 wires in porous silicon”, Phys. Rev. B, Vol. 45, pp. 856, 1992.
【33】 V. Lehmann, U. Gösele, “Porous silicon formation: A quantum wire effect”, Appl. Phys. Lett., Vol. 58, pp. 856, 1991.
【34】 R.L. Smith, S.F. Chuang, and S.D. Collins, “A theoretical model of the formation morphologies of porous silicon”, J. Electron. Mater., Vol.17, pp. 533, 1988.
【35】 R.L. Smith and S.D. Collins, “Generalized model for the diffusion-limited aggregation and Eden models of cluster growth”, Phys. Rev. A, Vol. 39, pp. 5409, 1989.
【36】 R.L. Smith and S.D. Collins, “Porous silicon formation mechanisms” J. Appl. Phys., Vol. 71, R1, 1992.
【37】 T.A. Witten and L.M. Sander, “Diffusion-limited aggregation” Phys. Rev. B, Vol. 27, pp. 5686, 1983.
【38】 V. Labunov, V. Bondarenko, I. Glinenko, A. Dorofeev and L. Tabulina ,“Heat treatment effect on porous silicon”, Thin Solid Films, Vol. 137, pp.123-134, 1986.
【39】 G. Müller, M. Nerding, N. Ott, H. P. Strunk, and R. Brendel,“Sintering of porous silicon”, phys. stat. sol. (a), Vol. 197, pp. 83-87, 2003.
【40】 Reza Abbaschian, Robert E., Reed-Hill, Physical Metallurgy Principles, 3rd Edition, PWS Kent Publishing Company, Boston, 1992.
【41】 Randall M. German, Sintering Theory and Practice, John Wiley & Sons Inc, New York, 1996.
【42】 N. Ott, M. Nerding, G. Mu¨ ller and R. Brendel, H. P. Strunk, “Evolution of the microstructure during annealing of porous silicon multilayers”, J.
Appl. Phys., Vol. 95, pp. 497-503, 2004.
【43】 M. Banerjee, E. Bontempi, S. Bhattacharya , S. Maji , S. Basu, H. Saha, 73
“Thermal annealing of porous silicon to develop a quasi monocrystalline structure”, J Mater Sci: Mater Electron, Vol.20, pp. 305-311, 2009.
【44】 Q.-Y. Tong and U. Gösele, “A model of low-temperature wafer bonding and its applications”, Journal of the Electrochemical Society143,(5), pp.1773-1779 ,1996.
【45】 Q.-Y. Tong, G. Cha, R Gafiteanu, and U Gösele, “Low temperature wafer direct bonding”, J. Microelectromech . Syst., vol. 3, pp. 29–35, 1994.
【46】小川洋輝，崛池靖浩著，“半導體潔淨技術”，顏誠廷譯，普林斯頓國際有限公司，臺北縣，2003.
【47】 Q.-Y. Tong, W.J. Kim, T.-H. Lee, and U. Gösele, “Low Vacuum Bonding”, Electrochemical and Solid-State Letters, Issue 1, pp. 52-53,1998.
【48】 G.L. Sun et al, “Cool plasma activated surface in silicon direct bonding technology”, J. de Physique, 49(C4),79, 1988.
【49】 D. Pasquariello, C. Hedlund, and K. Hjort, “Oxidation and induced damages in oxygen plasma in situ wafer bonding,” Journal of the Electrochemical Society, vol.147, pp. 2699–2702, 2000.
【50】 G. Wallis and D.I. Pomerantz, “Field Assisted Glass-Metal Sealing”, J. Appl. Phys. 40, 1969.

指導教授

李天錫(Tien-His Lee)

審核日期

2011-6-14

推文