雙圖案微影技術下考慮原生衝突之電路軌道繞線

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：22

、訪客IP：18.216.84.37

姓名

賴弼廷(Bi-Ting Lai) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

雙圖案微影技術下考慮原生衝突之電路軌道繞線
(Native-Conflict-Aware Track Routing for Double Patterning Technology)

相關論文

★ 三維積體電路的微凸塊分配與晶粒間繞線之研究	★ 考慮製造限制之繞線研究
★ 使用次序關係配置三維積體電路微凸塊	★ 考慮線長匹配的平行匯流排之逃脫繞線
★ 用於三維積體電路之溫度導向平面規劃的散熱型矽晶穿孔面積融合方法	★ 考量障礙物間通道寬度限制及避免電子遷移效應的繞線樹建構之研究
★ 三維積體電路中同步降低熱點溫度與電源雜訊之研究	★ 使用延遲決策技術於類比電路之可繞度導向擺置方法
★ 提升聚焦離子束對訊號探測能力之細部繞線方法	★ 考慮障礙物閃避及電荷分享之鑽孔數量最小化跳線插入演算法
★ 模組化層級三維積體電路之矽晶穿孔規劃與線長最佳化	★ 降低不匹配效應之力導向電容擺置方法
★ 考慮繞線資源需求之標準元件擺置合法化	★ Simultaneous escape routing for mixed-pattern signals on staggered pin arrays
★ 面積與最大線長最佳化之類比積體電路佈局產生器	★ 含多重檢查機制之實體驗證自動化工具

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

隨著製程的演進，積體電路的元件尺寸逐漸縮小，已經達到32 奈米製程。由於可印刷性和可製造性的問題，微影技術（lithography）遇到了瓶頸。雙圖案微影技術（double patterning lithography）被視為近來最適合改善32 奈米製程以下的技術。
雙圖案微影技術是基於目前的製程技術下，將每一層的整體佈局分解為兩個光罩以加大最小圖案間距和改善焦距深度。當發生圖案衝突（conflict）時，即遇到整體佈局無法被完整地分解為兩個光罩，就必須把單一佈局圖案切割成兩個次圖案，此分割動作造成同一個佈局圖案被分解到不同光罩而產生需要接合，我們稱此接合處為縫合圖案（stitch）。假如晶片平面上沒有足夠的空間插入縫合圖案以解決衝突，即產生了原生衝突（native conflict），此時，便需要曠日費時地進行佈局修正。目前的相關研究多著重在後佈局（post layout）階段或細部繞線（detailed routing）階段以降低縫合圖案和原生衝突的數目，然而隨著現今佈局的複雜度愈來愈高，如何在繞線階段提早考量雙圖案微影技術且不會增加細部繞線的負擔，將是一大挑戰。
本論文提出在軌道繞線（track routing）階段考量雙圖案微影技術。我們提出的方法不僅可以有效地降低原生衝突的數量，還可以加速後續細部繞線的處理時間。此外，我們提出虛擬節點（pseudo pin）的技術，不只可以在軌道繞線時避免大量的原生衝突，還可粗略地估計細部繞線的走向，幫助軌道繞線找出合適的繞線軌道以達到最短繞線路徑的目的。實驗結果顯示，本論文提出的方法在微幅增加繞線線長下，可大量地降低原生衝突數量，同時更可提高繞線的完成度。

摘要(英)

As the manufacturing process advances, the size of integrated circuits has shrunk into the 32 nm. Lithography process encounters a bottleneck due to printability and manufacturability issues. Recently, double patterning lithography（DPL）has been proposed for the most feasible solution for sub-32-nm node process.
To increase the half-pitch resolution and improve depth of focus, DPL decomposes a layout into two masks by using current infrastructures. The conflict of DPL means that a layout cannot be decomposed completely, and then the un-decomposable pattern must be partitioned into two sub-patterns. These two sub-patterns should be assigned to different masks and connected to each other. The touching edge of sub-patterns is called stitch. If there is no enough space to insert a stitch for the un-decomposable pattern, a native conflict is generated. A layout with native conflicts will result in layout modification. The current researches focus on reducing the number of stitches and the number of native conflicts in the post layout phase or detailed routing phase. Since the layout is more and more complicated, considering DPL before detailed routing and alleviating the loading in detailed routing will be a challenge.
In this thesis, we propose a method to consider DPL in track routing. Besides, we propose a pseudo pin technique to avoid generating a lot of native conflicts in track routing and predict the traces of detailed routing. Experimental results show that the proposed method not only minimizes the number of native conflicts significantly, but also reduces wirelength.

關鍵字(中)

★ 軌道繞線
★ 雙圖案微影技術

關鍵字(英)

★ double patterning technology
★ track routing

論文目次

摘要 .............................................................. i
Abstract.......................................................... ii
致謝 ............................................................ iii
目錄 ............................................................. iv
圖目錄 ........................................................... vi
表目錄 ........................................................... ix
第一章、緒論 ..................................................... 1
1-1 前言........................................................ 1
1-2 雙圖案微影技術的挑戰........................................ 3
1-3 研究動機.................................................... 4
1-4 問題描述.................................................... 9
第二章、相關研究 ................................................ 11
2-1 後佈局階段................................................. 11
2-2 細部繞線階段............................................... 18
2-2-1 以網格為基礎的細部繞線............................... 19
2-2-2 以無網格為基礎的細部繞線............................. 22
第三章、考慮原生衝突之電路軌道繞線 .............................. 26
3-1 考慮原生衝突之電路軌道繞線流程............................. 26
3-2 計算通道擁擠程度（Panel density calculation）................... 27
3-3 評估虛擬節點的位置（Pseudo pin prediction） ................... 28
v
3-3-1 虛擬節點位置的限制條件............................... 30
3-3-2 原生衝突的限制條件................................... 31
3-3-3 最小線長的限制條件................................... 33
3-4 線軌指派（Track assignment） ................................ 34
3-5 線段和繞線軌道之關係圖上邊的權重計算（Segment weight decision）
............................................................... 37
3-6 更新虛擬節點（Pseudo pin update） ............................ 39
第四章、實驗結果與分析 .......................................... 41
4-1 工作平台與測試檔說明....................................... 41
4-2 實驗結果與比較............................................. 41
第五章、結論 .................................................... 47
第六章、參考文獻 ................................................ 48

參考文獻

[1] International Technology Roadmap for Semiconductors
[2] Alfred Kwok-Kit Wong, Resolution enhancement techniques in optical lithography. SPIE Publications, 2001.
[3] Obert Wood, Chiew-Seng Koay, Karen Petrillo, Hiroyuki Mizuno, Sudhar Raghunathan, John Arnold, Dave Horak, Martin Burkhardt, Gregory Mcintyre, Yunfei Deng, Bruno La Fontaine, Uzodinma Okoroanyanwu, Anna Tchikoulaeva, Tom Wallow, James H.-C. Chen, Matthew Colburn, Susan S.-C.
Fan, Bala S. Haran and Yunpeng Yin,“Integration of EUV lithography in the fabrication of 22-nm node devices,”in Proc. of SPIE, vol. 7271, February 2009.
[4] Chang-Moon Lim, Seo-Min Kim, Young-Sun Hwang, Jae-Seung Choi, Keun-Do Ban, Sung-Yoon Cho, Jin-Ki Jung, Eung-Kil Kang, Hee-Youl Lim, Hyeong-Soo Kim and Seung-Chan Moon,“Positive and negative tone double patterning lithography for 50nm flash memory,”in Proc. of SPIE, vol. 6154, February 2006.
[5] Tsann-Bim Chiou, Robert Socha, Hong Chen, Luoqi Chen, Stephen Hsu, Peter Nikolsky, Anton van Oosten and Alek C. Chen,“Development of layout split algorithms and printability evaluation for double patterning technology,”in Proc. of SPIE, vol. 6924, February 2008.
[6] Andrew B. Kahng, Chul-Hong Park, Xu Xu and Hailong Yao,“Layout Decomposition for Double Patterning Lithography,”in Proc. of ICCAD, pages 465-472, November 2008.
[7] Yue Xu and Chris Chu,“GREMA: Graph Reduction Based Efficient Mask Assignment for Double Patterning Technology,”in Proc. of ICCAD, pages 601-606, November 2009.
[8] Yue Xu and Chris Chu,“A Matching Based Decomposer for Double Patterning Lithography,”in Proc. of ISPD, March 2010.
[9] Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan and David Z. Pan,“A New Graph Theoretic Multi Objective Layout Decomposition Framework for Double Patterning Lithography,”in Proc. of ASPDAC, pages 637-644, January 2010.
[10] Szu-Yu Chen and Yao-Wen Chang,“Native-Conflict-Aware Wire Perturbation for Double Patterning Technology,”in Proc. of ICCAD, pages 556-561, November 2010.
[11] Kun Yuan and David Z. Pan,“WISDOM: Wire Spreading Enhanced Decomposition of Masks in Double Patterning Lithography,”in Proc. of ICCAD, pages 32-38, November 2010.
[12] Jian Sun, Yinghai Lu, Hai Zhou and Xuan Zeng,“Post-Routing Layer Assignment for Double Patterning,”in Proc. of ASPDAC, pages 793-798, January 2011.
[13] Chin-Hsiung Hsu, Yao-Wen Chang and Sani Richard Nassif,“Template-Mask Design Methodology for Double Patterning Technology,”in Proc. of ICCAD, pages 107-111, November 2010.
[14] Chin-Hsiung Hsu, Yao-Wen Chang and Sani Rechard Nassif,“Simultaneous Layout Migration and Decomposition for Double Patterning Technology,”in Proc. of ICCAD, pages 595-600, November 2009.
[15] Minsik Cho, Yongchan Ban and David Z. Pan,“Double Patterning Technology Friendly Detailed Routing,”in Proc. of ICCAD, pages 501-511, November 2008.
[16] Kun Yuan, Katrina Lu and David Z. Pan,“Double Patterning Lithography Friendly Detailed Routing with Redundant Via Consideration,”in Proc. of DAC, pages 63-66, July 2009.
[17] Xin Gao and Luca Macchiarulo,“Enhancing Double-Patterning Detailed Routing With Lazy Coloring and Within-Path Conflict Avoidance,”in Proc. of DATE, pages 1279-1284, March 2010.
[18] Yen-Hung Lin and Yih-Lang Li,“Double Patterning Lithography Aware Gridless Detailed Routing with Innovative Conflict Graph,”in Proc. of DAC, pages 398-403, June 2010.
[19] Shabbir Batterywala, Narendra Shenoy, William Nicholls and Hai Zhou,“Track Assignment: A Desirable Intermediate Step Between Global Routing and Detailed Routing,”in Proc. of ICCAD, pages 59–66, November 2002.
[20] Di Wu, Jiang Hu, Min Zhao and Rabi Mahapatra,“Timing Driven Track Routing Considering Coupling Capacitance,”in Proc. of ASPDAC, pages 1156-1159, January 2005.
[21] Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen and Der-Tsai Lee,“Crosstalk- and Performance-Driven Multilevel Full-Chip Routing,”IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 24, no. 6, pages 869–878, June 2005.
[22] Yih-Lang Li, Hsin-Yu Chen and Chih-Ta Lin,“NEMO: A New Implicit-Connection- Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation,”IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 26, no. 4, pages 705-718, April 2007.
[23] http://eda.ee.ntu.edu.tw/research.htm
[24] http://www-01.ibm.com/software/integration/optimization/cplex-optimizer/

指導教授

陳泰蓁(Tai-Chen Chen)

審核日期

2011-8-15

推文