| 摘要(英) |
As the shrink of semiconductor process, the process variation effects performance of circuit much more seriously. It also causes high complexity and time-consuming on designing circuits. Therefore, layout automation is likely to play a key role in analog circuit design.
The performance of many types of analog circuits, like ADC, DAC, etc., relies on the implementation of accurate capacitor ratio. Generally, capacitor mismatch can result from two sources of error: random mismatch and system mismatch. Random mismatch is due to process variation, while system mismatch is mainly caused by asymmetrical layout and processing gradient. These will decrease the accuracy and yield of circuits. To reduce these negative effects, several smaller unit capacitors will be parallel connected to replace the whole bigger capacitor. The parasitic effect between each unit capacitor will also be considered.
In this thesis, a double-layer double-channel array capacitance equilibrium router is proposed for capacitor array block creation. By four steps: initial setting, capacitor placement, generation of interconnects, parasitic capacitor and compensation, the whole routing of circuit will be established. The router can be not only applied to the case of a pair of two target but also to the multiple target capacitors. By the conjunction of an array assignment using of spatial correlation feature, three cases are used as examples to demonstrate the assignment-routing flow. The first one is a case of two targets with a ratio of 1:1. The second one is a case of multiple targets with continuous ratio of 8:4:2:1:1. The last one is a case with non-integer ratio and compensation from parasitic effect, it also can provide an accurate ratio up to second digit after decimal point. After finishing layout creation, the wire parasitic capacitor will be extracted from Calibre. Finally, the accuracy of capacitor ratio and layout area will contrasted with a yield-aware ratio-keeping channel router which uses only vertical channel.
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| 參考文獻 |
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