在此篇論文裡，使用快速熱退火去形成鎳化矽的製程被研究。然後鎳化矽被應用於新穎的元件結構裡--自對準奈米線金氧半場效電晶體。自對準奈米線電晶體被製作在70奈米厚的絕緣層上矽的基版上，具有先進製程模組，包含凹陷式氮化矽間隙壁、完全鎳化矽源極與汲極、自對準多晶矽閘。為了讓元件在薄的絕緣層上矽的基版上，獲得低串聯電阻，利用完全鎳化矽源/汲極與最佳化間隙壁寬度製程可獲取效益。因為區域矽氧化法被整合在奈米線電晶體製程裡，我們不需用電子束微影去做精確的對準，即可獲得超窄的閘堆疊結構，使得自對準多晶矽閘技術有效的改善製程量率。由於熱磷酸濕蝕刻在氮化矽與矽之間有很高的選擇比，因此熱磷酸濕蝕刻被使用來實現凹陷式間隙壁。藉由凹陷式間隙壁，多晶矽化金屬的邊際效應被增強，導致於片電阻值被進一步的減少。最後，元件的效能被量測與分析。 In this thesis, the formation of NiSi silicide using rapid thermal annealing is investigated. The NiSi salicidation process is, then, incorporated into the fabrication of novel self-aligned nanowire MOSFET devices structure. A self-aligned nanowire MOSFET fabricated on a 70-nm-thick SOI wafer, features advanced process modules including recessed nitride spacer, fully silicided (NiSi) source/drain, and self-aligned poly silicon gate. In the pursuit of low series resistance in a thin SOI, it is critical to optimize spacer width and utilize fully-silicide S/D. Since LOCOS process is integrated in a nanowire MOSFET process flow, one doesn’t require e-beam lithography to do precise alignment for ultra narrow gate stacked structure. A self-aligned poly gate technology is utilized to improve manufacturing yield efficiently. A recessed spacer structure is carried out using hot phosphoric acid etching, which is highly selective between Si3N4 and Si. Edge effects of Ni polycide formation are enhanced by such recessed spacer and result in Rs reduction further. Finally, the device performance is evaluated.
