應用於毫米波射頻接收機前端積體電路之研製; Design and Implementation of RF Receiver Front-end Integrated Circuits for Millimeter-wave Applications

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/10011

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Title:	應用於毫米波射頻接收機前端積體電路之研製;Design and Implementation of RF Receiver Front-end Integrated Circuits for Millimeter-wave Applications
Authors:	邱景鴻;Ching-Hung Chiu
Contributors:	電機工程研究所
Date:	2006-06-08
Issue Date:	2009-09-22 12:03:25 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	本論文在於討論設計與實現射頻接收機前端之電路，如低雜訊放大器，混波器和壓控振盪器。我們使用台積電0.18微米金氧半互補式 (CMOS) 製程來研製一個應用於K頻帶的增益可變式之低雜訊放大器。我們使用共平面波導 (CPW) 傳輸線做為匹配元件，以減低損耗性矽基板在高頻下的影響。在電路的高增益模式中，量測到的小訊號增益為8.1 dB，而雜訊指數為6 dB。本增益可變式之低雜訊放大器的增益可變範圍是7.2 dB。在本論文中也呈現設計了一個應用於3到34 GHz的分散式汲極混波器。這個混波器電路是使用了0.15微米共源單閘極的假型高速電子移動電晶體 (PHEMT) 來組成的一個簡單分散式架構，並且其轉換損耗在3到34 GHz之間均優於6.7 dB。本分散式混波器實現了低功率消耗和高線性度於寬頻的應用上。之後利用0.18微米CMOS製程技術來設計一個應用於26 GHz低相位雜訊且寬頻率調整範圍的PMOS交越耦合雙推式的壓控振盪器 (VCO)。電路中使用了一個只有PMOS的交越耦合對來降低相位雜訊，而其所量測到於二次諧波輸出端的相位雜訊在1 MHz位移時為-102.86 dBc/Hz。並且這個雙推式的VCO可達到14%的寬頻率調整範圍。另一個應用於50 GHz的雙推式VCO是使用了0.15微米PHEMT的製程技術所製作和使用一段λg/2長的微帶線共振器來達到雙推式振盪。這種類型的雙推式VCO擁有著簡單架構與良好特性的優點。由模擬結果，本VCO具有1.2 GHz的頻率調整範圍和在1 MHz位移時有-111.8 dBc/Hz的相位雜訊。 The thesis investigates the design and implementation of RF receiver front-end circuits, such as low noise amplifier, mixer, and voltage-controlled oscillator. A K-band variable-gain low noise amplifier (VGLNA) is designed and implemented using TSMC 0.18-μm CMOS technology. Coplanar waveguide (CPW) transmission lines are adopted as matching elements to reduce the effect of lossy silicon substrate at high frequency. In high-gain mode, the measured small signal gain of VGLNA is 8.1 dB and noise figure of 6 dB at 21.7 GHz. The gain control range of the VGLNA is 7.2 dB. A 3-34 GHz distributed drain mixer using CPW technology is demonstrated in this thesis. This MMIC mixer uses a simple distributed topology that is composed of common-source single-gate 0.15-μm PHEMT, and it shows a conversion loss of better than 6.7 dB from 3 to 34 GHz. This distributed mixer achieves low dc power consumption and high linearity for broadband applications. Afterward, the 26-GHz PMOS cross-coupled push-push VCO using 0.18-μm CMOS technology is design for low phase noise and wide tuning range. The PMOS-only cross-coupled pair is used to lower the phase noise, and the measured 2nd harmonic phase noise is -102.86 dBc/Hz at 1-MHz offset. The push-push VCO achieves a wide tuning range of 14%. Another 50-GHz push-push VCO uses 0.15-μm PHEMTs technology and the λg/2 microstrip line resonator to form a common resonator for push-push oscillation. This type of push-push VCO has the advantages of simple configuration and good performances. From simulated results, the VCO achieves the frequency tuning range of 1.2 GHz and the phase noise of -111.8 dBc/Hz at 1-MHz offset.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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