三元內容定址記憶體(TCAM)在數位系統中扮演著重要的角色，尤其是網路應用。與隨機存取記憶體相比，三元內容定址記憶體的主要缺點是較高的功率消耗。因此，有效降低功率的技術對於設計三元內容定址記憶體是非常重要的。 本論文提出了一個用於TCAM之低功率消耗設計技術。我們提出一個雙倍疊乘-累加命中線(DPS match line)架構以減低TCAM比對時的功率消耗。在DPS match line上，Pai電路實現NAND功能以減少Sigma電路的預充電機率，而Sigma電路則是實現NOR功能。如此DPS match line的功率消耗可以被減少。此外，N位元的Pai電路將被分成兩個N/2位元的平行運算電路以減少Pai電路的延遲時間。與NOR-type命中線比較，利用此命中線完成之32x64三元內容定址記憶體，可降低60%的功率消耗。 另外，一個改進的高優先權編碼器亦被提出來消除典型高優先權編碼器的DC電流。模擬結果顯示出此電路的功率消耗只為典型高優先權編碼器的77%。本論文針對TCAM亦提出了一個二維備份電路設計方式所提出的方法可以關閉缺陷元件的預充電動作，如此修復後的TCAM比起完好的TCAM將不會造成多餘的功率消耗。 Ternary content addressable memories (TCAMs) play an important role in many digital systems, especially for network applications. Compared with the random access memory (RAM), however, high power dissipation is one of major disadvantages of the TCAMs. Thus, efficient power-reduction techniques are very important for designing a cost-efficient TCAM. This thesis proposes a low-power design technique for TCAMs. A double Pai-Sigma (DPS) match line structure is proposed to reduce the Compare power of a TCAM. In a DPS match line, the Pai circuit realizing a NAND function can reduce the precharging probability of the Sigma circuit which realizes a NOR function, such that the power consumption of the DPS match line is reduced. To reduce the delay of the Pai circuit, furthermore, an N-bit Pai circuit is designed as two N/2-bit Pai circuits in parallel. Compared with a TCAM with NOR-type match lines, simulation results show that 60% power reduction can be achieved for a 32x64-bit TCAM with the double Pai-Sigma match lines. On the other hand, a modified priority encoder is also proposed to eliminate the DC current of a typical priority encoder. Simulation results show that the modified priority encoder only consumes about 77% power of a typical priority encoder. This thesis also presents a two-dimension redundancy scheme for TCAMs. The proposed redundancy scheme can turn off the precharge operation of defective elements, such that a repaired TCAM does not consume more power than a good one.
