隨著半導體製程之進步，積體電路發展已驅向系統單晶片化。當系統整合於同一晶片時即需要準確的時脈訊號，通常會選用鎖相迴路來當做參考時脈來源。因此鎖相迴路是單晶片系統中重要同步單位，而其時脈之抖動特性即為其重要效能。以往測試鎖相迴路效能多用外部儀器來做時脈抖動量測，但是今日因鎖相迴路操作頻率之提升，測試儀器成本大大提高。此外利用儀器量測時外部雜訊亦會干擾測試結果，因此產生了內建時脈抖動量測電路。 本論文提出的內建時脈抖動量測電路以減少測試時間、晶片面積及降低雜訊影響為設計目標。我們以游標尺延遲線電路加上自我取樣方法來實現時脈抖動量測電路。電路分為二級，首先由一週期延遲電路將時脈訊號快速延遲一週期，接著利用抖動量測電路做抖動量測。加上一週期延遲電路後即不再需要參考時脈，量測結果可不受參考時脈雜訊影響，並且能減少電路硬體消耗及加快測試時間。 此時脈抖動量測電路是利用聯電90奈米製程，完成一應用於2.5GHz鎖相迴路之內建時脈抖動量測電路，電路解析度為5.3ps。 As the improvement of semiconductor technology, System-On-Chip(SOC) is the current trend of VLSI circuit. When many systems were integrated into a chip, the reference clock signal must be accurate. We usually choose Phase-Locked Loop(PLL) circuit as the reference clock source. Since PLL is the essential synchronization element in SOC, the jitter characteristic is the most important property. In the past, the jitter was measured by the external equipment. But with the increase of PLL operating frequency, the cost of test equipment has greatly raised. Besides, the external equipment may induce noise, so the built-in self test circuit is proposed. The design purpose of this thesis is designing a built-in self test circuit with less test time, smaller chip area and lower power noise effect. We use vernier delay line circuit with self-sample method to accomplish this work. The circuit is composed of two stages. The first stage is one period delay circuit. It can delay input clock signal one period rapidly. The second stage is jitter measurement circuit. It has high resolution when measuring jitter. With the one period delay circuit, the measurement result will not be affected by the reference clock noise, reduce some chip area and speed up the test time This built-in self test circuit for 2.5GHz PLL is implemented in UMC 90nm CMOS technology, the circuit resolution is 5.3ps.
