現今的積體電路(IC)設計已邁入深次微米(deep-submicron)時代，隨著元件尺寸(device size)不斷的縮小，許多製程上所衍生出來的效應會明顯的影響到整個積體電路的製造結果，對於類比電路來說這些影響更加的顯著。因此可製造性導向設計(Design for Manufacturability, DFM)或良率導向設計(Design for Yield, DFY)，在近年來變成很熱門的話題。其主要的概念，是希望IC設計者在設計初期，把製造過程中可能發生的製程漂移(process variation)現象考慮進來，利用元件參數的變異分析(variation analysis)，事先評估對電路效能的影響，期望能設計出容忍度(tolerance) 更佳的電路，以提升良率、降低成本。 常見的製程漂移分析方法，是利用統計分析(statistical analysis)的概念來做蒙地卡羅模擬(Monte Carlo Simulation)。只要知道元件參數在統計上變異的情況，透過蒙地卡羅分析，經由幾百次或幾千次的模擬，便能預估製程漂移對於電路效能影響的分佈，幫助設計者早期評估可能出現的良率結果。然而，過去的蒙地卡羅分析是採用低階層模擬(low level simulation)的方式，如HSPICE。但是這樣的低階模擬太過耗時，所需的時間對於有上市壓力的業界來說，更是難以接受。 本論文便是針對製程漂移敏感(sensitive)的類比電路，以最常用的鎖相迴路(PLL)為研究實例，成功的提出一套有效方法來建立精準的類比電路行為模型(behavioral model)。這個模型能夠反應製程漂移對電路效能的影響，只要IC製造商(foundry)提供相關的元件變異模型，那麼我們就能使用這樣的電路行為模型，利用高階(high level)的模擬方式，來加快統計分析的速度，早期預估可能的良率結果，進而避免盲目的下線(tape out)、減少再次製作光罩的成本。除了加快模擬速度之外，我們的模型也有不錯的精準度，期望能取代傳統費時的電晶體階層蒙地卡羅分析，來幫助設計者更有效率的進行製程變異對電路影響之統計分析。 With the shrinking of device size in deep submicron process, impacts of process variation for circuit performance are more and more important, especially for analog circuits. Therefore design for manufacturability (DFM) and design for yield (DFY) become popular research topics. The consideration of process variation effects is the main issue of DFM and DFY. If we can use the device parameter variation analysis to evaluate the circuit performance due to the process variations in the beginning of designing a circuit system, we will get better tolerance to increase yield rate and reduce production cost. In order to analyze the impacts of process variations, one of the common approaches is using Monte Carlo (MC) analysis. According to the statistical model of transistor parameters, lots of samples are selected with different parameter values to perform transistor-level simulations and observe the shift of output performance. If the number of samples is large enough, this approach can accurately estimate the impacts of process variations. However, since transistor-level simulation often required long simulation time, repeating hundred times of simulations are too expensive for time to market. In this thesis, we propose an efficient way to build an accurate analog behavioral model for phase locked loop (PLL) circuit, which is more sensitive in performance due to process variations. This behavioral model can reflect the performance shift under process variations with this behavioral model, we can use the device variation model from foundry to conduct a high-level Monte Carlo analysis and reduce the simulation time significantly. Besides the speed improvement over HSPICE simulation, our approach also has good accuracy. Therefore, this approach can help designers to estimate the effects of process variations more efficiently.
