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http://ir.lib.ncu.edu.tw/handle/987654321/10098
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| 題名: | 無線寬頻系統之前端接收機與頻率合成器暨V頻段除頻器之研製;The Implementations on Wireless System of Wide-Band Front-End Receiver, Frequency Synthesizer, and V Band Frequency Divider |
| 作者: | 陳憲瑞;Hsien-Jui Chen |
| 貢獻者: | 電機工程研究所 |
| 關鍵詞: | 接收機;頻率合成器;除頻器;Receiver;Frequency Synthesizer;Frequency Divide |
| 日期: | 2007-07-04 |
| 上傳時間: | 2009-09-22 12:06:39 (UTC+8) |
| 出版者: | 國立中央大學圖書館 |
| 摘要: | 本論文係以TSMC 0.18-μm CMOS製程與TSMC 0.13-μm CMOS製程，研製應用於超寬頻（Ultra Wideband）系統之前端接收機、頻率合成器以及應用於V頻段之注入式鎖定除三除頻器。 第一部份為超寬頻接收機，此電路包含低雜訊放大器及混頻器。低雜訊放大器選用電阻並聯負回授來達成寬頻之需求。此外，電路中加入一電感來改善高頻增益衰減的問題。而為了達到寬頻輸入阻抗匹配，混頻器之轉導極加入了一負回授電阻。實驗結果顯示出，整體接收機之轉換增益為19.29 ~ 17.12 dB（Single-ended），輸入反射損耗最差小於-6.7 dB。雜訊指數於中頻100 MHz量得值為5.25 ~ 6.89 dB (DSB)。1-dB壓縮點為-24 ~ -28 dBm。三階截斷點為-7 ~ -11 dBm。LO-IF隔離度為-44 ~ -57 dB，LO-RF隔離度為-52.5 ~ -77 dB，RF-IF隔離度為-19.6 ~ -59 dB，整體電路之功率損耗為29.1 mW。 第二部份為超寬頻頻率合成器，此電路包含四相位壓控振盪器（QVCO）、電流模式邏輯（CML）除頻器、真單一時脈（TSPC）除頻器、頻率選擇器（Frequency Selector）、單端頻帶混頻器（SSB Mixer）、相頻檢測器（PFD）、充電泵（Charge Pump）、迴路濾波器（Loop Filter）。在壓控振盪器的部份，為了防止製程變異所導致振盪頻率偏移，加入了二進位加權開關，並提出了一適用於選擇開關電容以及變容器數值之經驗方程式。此外，為了提高頻率選擇器之隔離度，於電路中加入了複製（Dummy）電晶體。實驗結果顯示出，此電路可產生6個頻帶之訊號源以提供予UWB系統使用。整體迴路之相位雜訊在振盪頻率8.448 GHz差頻1MHz處，其值為-103.51 dBc/Hz。而在差頻10 kHz處，相位雜訊為-80.53 dBc/Hz。整體迴路之鎖住時間（Settling Time）大約為10 μs。頻帶間切換時間<1 ns。6336 MHz頻段其旁帶抑制量為-37.75 dBc。整體電路之功率損耗為93.4 mW。 第三部份為60 GHz注入式鎖定除三除頻器，其中包含兩個不同的架構。架構一之除頻器實驗結果如下，當Vtune從0 V改變至1.8 V，注入訊號功率為5 dBm時，其可除頻率範圍為58.02 ~ 65.99 GHz。當Vtune固定於1.8 V，注入訊號功率為5 dBm時，單點電壓（@Vtune = 1.8 V）之鎖住範圍為180 MHz。此除頻器電路與緩衝放大器之直流功率損耗分別為1.395 mW及3.48 mW；第二個架構為改良第一種架構之除頻器，與第一種架構之不同處為，此除頻器未加入前置放大器，而改用變壓器直接注入之方式，有效提高注入效率，增加鎖住範圍。架構二之除頻器實驗結果如下，當Vtune從0 V改變至1.8 V，注入訊號功率為5 dBm時，其可除頻率範圍為56.5 ~ 66.4 GHz。當Vtune固定於1.8 V，注入訊號功率為5 dBm時，單點電壓（@Vtune = 1.8 V）之鎖住範圍為1750 MHz。此除頻器電路與緩衝放大器之直流功率損耗分別為3 mW及3.85 mW。 The thesis presents an Ultra Wideband (UWB) receiver front end, frequency synthesizer and V band injection locked frequency divider, which are implemented in TSMC 0.18-μm and 0.13-μm CMOS technologies, respectively. The functional block of Ultra wide band (UWB) receiver front end includes a low noise amplifier (LNA) and a mixer. The low noise amplifier employs the RC shunt feedback technique for broadening the bandwidth. Besides, an inductor is used as an interstage matching at the cascode LNA which efficiently improve the flatness of the cascode LNA. The RC shunt feedback is applied to the gm stage of mixer for input impedance matching of reveiver. The experimental results of the receiver are a conversion gain of 19.29 ~ 17.12 dB (Single-ended), an input return loss better than 6.7 dB, a noise figure of 5.25 ~ 6.89 dB (DSB) at 100 MHz IF frequency, 1-dB compression point of -24 ~ -28 dBm, an input third order intercept point of -7 ~ -11 dBm, an LO-IF isolation of -44 ~ -57 dB, an LO-RF isolation of -52.5 ~ -77 dB, an RF-IF isolation of -19.6 ~ -59 dB. The total power consumption is 29.1 mW. The circuit block of ultra wideband (UWB) frequency synthesizer includes a quadrature voltage control oscillator (QVCO), a current mode logic (CML) divider, a true single phase clock (TSPC) divider, a frequency selector, a single sideband mixer (SSB Mixer), a phase frequency detector (PFD), a charge pump and a loop filter. The experimental results show that the designed sysnthesizer generates six bands for the local signals in UWB transmitter system. In the VCO design, the binary weighted band switching capacitor is used to calibrate the frequency drifting under process variations. Beside, a useful formula is proposed to choose the value of varactor and band switching capacitor. In frequency selector deisgn, the proposed dummy transistor is added to improve isolation. The measured close loop phase noise is -103.51 dBc/Hz at 1 MHz offset and -80.53 dBc/Hz at 10 kHz offset in 8.448 GHz band. The settling time of this loop is about 10 μs. The switching time between two sub-bands is small then 1 ns. The sideband suppression is low as -37.75 dBc in the 6336 MHz band. The total power consumption of the synthesizer is 93.4 mW. Two injection locked frequency dividers was investigated in this study. In the first injection locked frequency divider, the obtained locking range is 180 MHz with injection power of 5 dBm at Vtune of 1.8V. The total loacking range of divider is from 58.02 ~ 65.99 GHz which is correspondent to a locking range of 7.97 GHz while varying Vtune from 0 V to 1.8 V. The power consumption of core circuit and buffer amplifier is 1.395 mW and 3.48 mW, respectively. The second topology of frequency divider is the improvement version with respect to the first one. The difference between these two dividers is the second topology of frequency divider without using preamplifier, instead of the proposed transformer direct injection method to improve injection efficiency and locking range. The second proposed ILFD achieved the locking range of 1.75 GHz at the injection power of 5 dBm and Vtune of 1.8 V. The total locking range of the divider is from 56.5 to 66.4 GHz which is correspondent to a locking range of 9.9 GHz while varying Vtune from 0 V to 1.8 V. The power consumption of core circuit and buffer amplifier is 3 mW and 3.85 mW, respectively. |
| 顯示於類別: | [電機工程研究所] 博碩士論文
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