運算放大器之自動化設計流程及行為模型研究; An Automation Flow of OP Amplifier Design with Accurate Behavior Model

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Title:	運算放大器之自動化設計流程及行為模型研究;An Automation Flow of OP Amplifier Design with Accurate Behavior Model
Authors:	趙晏廷;Yen-Ting Chao
Contributors:	電機工程研究所
Keywords:	運算放大器;自動化設計;行為模型;Automation Flow;Behavior Model;OP Amplifier
Date:	2007-07-04
Issue Date:	2009-09-22 12:06:46 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	本論文提出一個自動化設計運算放大器的流程，並提供四種常用架構的運算放大器：伸縮(telescopic)、摺疊疊接 (folded cascade)、電流鏡(current mirror)、雙級 (two stage)。整套流程已經以C++實現並連結HSPICE輔助設計。使用者只需要輸入需求的規格及選擇運算放大器的架構，便可以得到符合規格的電路。放大器是類比電路中基本的元件，並且在很多電路中都被廣泛應用。自動化設計運算放大器的流程將加速類比電路的設計，降低類比電路的設計時間。隨著CMOS製程技術的下降，由於超大型積體電路(VLSI)複雜度的增加，以及SoC (System on Chip)的發展，驗證電路設計的正確性變的比以前困難，模擬時間也隨之上升。為了減少模擬的時間，提供所需的放大器的同時，也提供了一個運算放大器的行為模型，可以在行為模式模擬電路，驗證整體系統的正確性。 An automation flow of OP Amplifer design is proposed in this thesis. Four common OP Amplifers topologies: telescopic、folded cascade、current mirror and two stage are supported in this flow. It has been implemented by C++ program and HSPICE. Given the required specification and target topology, the tool will offer the circuit with detailed sizes that meets the required specification in the choosed topology. OP Amplifers are the fundamental components in analog circuits that have been used in many kinds of circuits extensively. An automation flow of OP Amplifer design can greatly decrease the design time of the analog circuit. As CMOS process technology scales, the increasing complexity of VLSI systems also increase the simulation time and verification efforts. In order to reduce the simulation time, the behavioral models of the generated OP circuits are provided simultaneously, which can be used to verify the behavior of the entire system at behavioral level to reduce the system simulation time.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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