應用於V頻段射頻接收機前端電路之研製; Implementation of RF Receiver Front-End Circuits for V-Band Applications

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題名:	應用於V頻段射頻接收機前端電路之研製;Implementation of RF Receiver Front-End Circuits for V-Band Applications
作者:	楊家軍;Chia-Chun Yang
貢獻者:	電機工程研究所
關鍵詞:	低雜訊放大器;壓控振盪器;次諧波混頻器;星行混頻器;LNA;star mixer;VCO;sub-harmonic mixer
日期:	2007-07-04
上傳時間:	2009-09-22 12:09:46 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	本論文係以WINTM 0.15-μm pHEMT與TSMC 0.18-μm CMOS製程，研製應用於V頻段射頻接收機前端電路。主要設計電路包含低雜訊放大器、變壓器回授式壓控振盪器、次諧波電阻性混頻器與星形雙平衡混頻器。次諧波電阻性混頻器，電路中包含在LO端使用的堆疊式馬遜平衡器與在RF端使用的微小型功率分配器。跟一般平面式的馬遜平衡器相比使用堆疊式馬遜平衡器主要是提高耦合量，以便獲得低的介入損耗與小的面積。而功率分配器是使用縮小尺寸的技術縮減原本需要的四分之一波長的傳輸線。綜合以上原因，此混頻器可獲得較小的晶片面積。星形雙平衡混頻器，電路中含有兩個小型化的對偶巴倫。縮小化的對偶巴倫是使用並電容在電路中的輸入、輸出或終止端。於此電路中對偶巴倫的微小化設計，相較於基本型之對偶巴倫將節省60%的面積，因此得到一個極小面積之星形雙平衡混頻器。各電路之量測特性如下：低雜訊放大器方面：52.7 GHz的三級串接低雜訊放大器增益為13.59 dB，輸入反射損耗為11.76 dB，輸出反射損耗為12.81 dB，而輸入1 dB壓縮點為-12 dBm，模擬之雜訊指數在60 GHz為4.06 dB。壓控振盪器方面：26.2 GHz變壓回授式壓控振盪器，頻率可調範圍為473 MHz，輸出功率為-4.76 ~ -1.83 dBm，離主頻1 MHz之相位雜訊為-100.3 dBc/Hz，振盪器本身消耗功率為9.6 mW。混頻器方面: 次諧波電阻性混頻器於射頻頻率60 GHz時的轉換損耗為14.96 dB，輸入1-dB壓縮點為10 dBm，輸入三階交互調變交叉點為28 dBm，本地振盪對中頻訊號隔離度大於35 dB，本地振盪對射頻隔離度大於35 dB，射頻對中頻隔離度大於19 dB，晶片面積為0.99 × 0.82 mm2;星形雙平衡混頻器於射頻為60 GHz時，量測得到的轉換損耗為8.99 dB，輸入1-dB壓縮點為8.27 dBm，本地振盪對中頻訊號隔離度大於24 dB，本地振盪對射頻隔離度大於20 dB，射頻對中頻隔離度大於35 dB，晶片面積為0.68 × 0.59 mm2。 The thesis presents the of RF front-end circuits for V-band receiver, which are both implemented on WINTM 0.15-μm pHEMT and TSMC 0.18-μm CMOS technologies. The implemented circuits include a low noise amplifier, a transformer feedback voltage controlled oscillator, a sub-harmonically pumped resistive mixer, and a doubly balance star mixer. The sub-harmonically pumped resistive mixer includes an LO stacked Marchand balun and a miniaturized RF power divider. The stacked layout for LO balun is used to increase the coupling factor and obtain the low insertion loss and compact size which commonly used in planar balun. The RF power divider utilizes the reduce-size technique to miniaturize the required λ/4 transmission line. Therefore, the mixer accomplishes a compact chip size, for instance, the doubly balanced star mixer was realized by two proposed dual baluns and achieved a very compact form factor. The reduced sized dual balun can be simply realized by shunting overlay capacitance at the input, output, or end of balun. The designed miniature dual balun can save more than 60% chip area in comparison to that in conventional dual balun. In low noise amplifier, a 52.7 GHz three cascade stages low noise amplifier achieved a power gain of 13.59 dB, input/output return losses of 11.76 dB and 12.81 dB, respectively. The measured 1-dB gain compression point was -12 dBm, and simulated noise figure was 4.06 dB at 60 GHz. In voltage controlled oscillator, a 26.2 GHz transformer feedback voltage controlled oscillator obtained a tuning range of 437 MHz, an output power of -4.76 ~ -1.83 dBm. A -100.3 dBc/Hz phase noise at 1 MHz offset frequency was measured under the power consumption of 9.6 mW. In mixer design, a 60 GHz sub-harmonically pumped resistive mixer achieved the conversion loss of 14.96 dB, a input 1-dB gain compression point of 10 dBm, an input third order intermodulation intercept point of 28 dBm, an LO to IF isolation of better than 35 dB, an LO to RF isolation of greater than 35 dB, an RF to IF isolation of greater than 19 dB. The chip area yields a compact size less than 0.99 × 0.82 mm2. A 60 GHz doubly balanced star mixer achieved a conversion loss of 8.99 dB, an input 1-dB gain compression point of 8.27 dBm, an LO to IF isolation of better than 24 dB, an LO to RF isolation of greater than 20 dB, an RF to IF isolation of greater than 35 dB. The fabricated chip area is only 0.68 × 0.59 mm2.
顯示於類別:	[電機工程研究所] 博碩士論文

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