具寬頻操作及可程式化責任週期之數位同步電路; A Wide-Range Digital Synchronous Buffer with Programmable Duty Cycle

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題名:	具寬頻操作及可程式化責任週期之數位同步電路;A Wide-Range Digital Synchronous Buffer with Programmable Duty Cycle
作者:	陸曉文;Siao-Wun Lu
貢獻者:	電機工程研究所
關鍵詞:	延遲鎖定迴路;同步映射延遲電路;脈波寬度控制迴路;鎖相迴路;Delay- Locked Loop;Synchronous Mirror Delay;Pulse Width Control Loop;Phase-Locked Loop
日期:	2008-01-15
上傳時間:	2009-09-22 12:10:08 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	在現今單晶片系統設計的晶片中，含大量電路及廣佈時脈訊號網路，因此同步系統時脈是一個重要的考量，時脈偏斜所造成時脈不同步現象將嚴重威脅系統運作的正確性，而在許多電路設計架構中，除了時脈訊號同步的問題外，時脈訊號之責任週期(Duty Cycle, DC)也需要被精準的控制，以提高某些電路操作之可靠度、正確性，例如管線系統、雙倍取樣率記憶體(Double Data Rate, DDR )、雙取樣類比對數位轉換器(Double-Sampling ADC)等，在高頻時責任週期準確度與時脈同步將更重要。因此鎖相迴路(Phase-Locked Loop, PLL)和延遲鎖定迴路(Delay- Locked Loop, DLL)被提出用於相位的校準，而脈波寬度控制迴路(Pulse Width Control Loop, PWCL)則被提出用於校正責任週期。本論文提出了具寬頻操作及可程式化責任週期之數位同步電路(A Wide-Range Digital Synchronous Buffer with Programmable Duty Cycle)，此電路結合同步電路及脈波寬度控制迴路，以數位的方式設計同步電路，以改善鎖相迴路和延遲鎖定迴路鎖定時間較長的問題，採用高線性度可預設脈波寬度之脈波寬度控制迴路校正脈波寬度及程式化輸出責任週期。電路中利用頻率偵測器控制多段延遲線達到縮減電路面積、較寬的操作頻率以及節省功率消耗的效果，並使用額外的單擊電路取代原始單純的延遲線，使可程式化責任週期之數位同步電路的輸入脈波寬度範圍增加至10%~90%。具寬頻操作及可程式化責任週期之數位同步電路使用CMOS 0.18μm 1.8V製程並進行HSPICE模擬，操作頻率能夠操作在200MHz ~ 600MHz之間。當輸入頻率為600MHz時，輸入脈波寬度範圍可從10%到83%，而在200MHz時，輸入脈波寬度範圍可從10%到90%。輸出責任週其可由數位程式控制從35%到70%，其間格為5%。此電路完成相位及脈波寬度鎖定時間小於250ns，其鎖定後相位誤差小於±17ps及責任週期誤差小於±1% 。省電模式的功率消耗在600MHz時為12.3mW，比未加省電機制時減少了35.9%，核心面積約為0.11mm^2。 In view of the current SOC systems, a great deal of circuits is integrated on a chip and the clock signal is entirely distributed to synchronize the SOC systems. The clock synchronization circuits, hence, become an important issue. Clock skew will seriously influence system operating correctness. In addition to clock skew issue, the clock duty cycle also needs precise control to improve the reliability and correctness of circuit operation in some circuits, such as pipeline system, DDR, double-sampling ADC, etc. The clock synchronization and the precision of duty cycle are more important in high frequency applications. Therefore, phase-locked loop (PLL) and delay-locked loop (DLL) have been applied in many systems to deskew the clock phase. The pulsewidth control loop (PWCL) can be used to correct the clock duty cycle. In this thesis, a wide-range digital synchronous buffer with programmable duty cycle is proposed. This digital synchronous buffer combines digital synchronized delay circuit with the PWCL. The digital synchronized delay circuit solves the long tracking time problem of PLL and DLL. The high linearity PWCL with programmable duty cycle correction correct and program output duty cycle. The multi-band delay lines are used to reduce the chip area, widen the operation frequency and save power consumption. The one shot circuit adds in the delay line to make wide-range digital synchronous buffer achieve high input duty cycle range from 10% to 90%. The wide-range digital synchronous buffer with programmable duty cycle is implemented in 0.18μm CMOS 1.8V process. Based on HSPICE simulation, the operation frequency range is form 200MHz to 600MHz. The input duty cycle range is from 10% to 83% in 600MHz and from 10% to 90% in 200MHz. The preset output duty cycle range is form 35% to 70% in steps of 5%. The locking time is less than 250ns when phase and duty cycle are locked. The phase error is less than ±17ps and the duty cycle error is less than ±1%. The power consumption is 12.3mW in save power mode that is less than normal mode about 35.9%. The core area is about 0.11mm^2.
顯示於類別:	[電機工程研究所] 博碩士論文

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