| 摘要: | 本論文囊括二個不同的部份：第一部份探討低功率設計中的絕熱邏輯，並提出一改良之架構；第二部份為高效能靜態隨機存取記憶體的設計。 互補能量路徑絕熱邏輯 (CEPAL)改良半靜態能量回復邏輯 (QSERL)，透過增加一組充、放電的電晶體，產生互補的充、放電路徑。其電路使用單一互補弦波、以不需要相位交錯的多級結構、輸出端有著類似傳統CMOS電路的靜態特性為特色。CEPAL比起QSERL，有效縮短了輸出端的浮接時間，並具有更好的抗漏電流能力、雜訊容忍度、負載推動能力與製程穩定度。 本文更將所提出之CEPAL應用在序向電路中不可或缺的D型正反器上，以TSMC 0.18-um CMOS製程進行模擬，當電路操作於25 MHz時，CEPAL比起QSERL能節省多達60%的總體能量效益，搭配吾人所提出的“共用概念 (share scheme)”，在實現CEPAL電路上，能有著相同於實現QSERL電路的面積花費。 在本文的另一部份-靜態隨機存取記憶體之設計，吾人主要在於改變架構中的記憶單元、寫入電路與感測放大器。吾人先提出改變記憶單元中元件的外觀比以增加栓鎖資料的抗雜訊能力；之後，更進一步提出利用縮小寫入資料的電壓擺幅，以降低寫入時的功率損耗，再透過等電位訊號取代預充電的操作，提升讀取時的感測速度。吾人設計並模擬一4 kb的靜態隨機存取記憶體(使用Cadence及Hspice)，在供應電應為1.8 V與時脈頻率為1 GHz的操作情況下，8位元資料的輸出訊號均可達500 MHz，晶片整體(含輸出緩衝器)的功率損耗為8.932 mW，所設計之4 kb記憶體已透過國家晶片中心完成晶片下線製造。 This thesis embraces two different themes. The first is the improvement in adiabatic logic for low-power design. The other is on the design of an efficient static random access memory (SRAM). With reference to the first part, a structure called complementary energy path adiabatic logic (CEPAL) is proposed to improve the insufficiency of quasi-static energy recovery logic (QSERL). CEPAL employs respectively one additional transistor in its charging / discharging paths, compared to the QSERL counterpart, such that it can be with complementary energy paths. In addition, two complementary sinusoidal power clocks are used to achieve static CMOS characteristics. The two sinusoidal clocks do not require complex clocking schemes. CEPAL shortens substantially the time with respect to output floating, and has better fault tolerance, static noise margin, driving ability, and tolerance to process variation than QSERL. In addition to the presented logic style, CEPAL was further applied to D flip-flop that is essential to the sequential circuits. We studied the properties of interest by means of a 0.18-um CMOS process. The CEPAL DFF achieves an energy saving of 60% compared to its QSERL counterpart when operating at 25 MHz. With the proposed share scheme, the two logic styles can have the same area cost in terms of the designed circuits. As for the design of the SRAM, cell, write circuit and sense amplifier are of major improvement. In this part, we first propose to vary the cell aspect ratio so as to improve its static noise margin. We then propose to reduce the power loss during the write operation through shrinking the voltage swing on writing in data. Notably, we improve the sensing speed on read through using “equalizing” in place of the “precharging” in bit lines. We have designed and simulated a 4-kb SRAM using Cadence environment and Hspice. Simulation results show that while the designed 4-kb SRAM is set up at 1-GHz clock and nominal 1.8-V DC power supply, the 8-bit data outputs can have up to 500-MHz speed, with a total power consumption (including the output buffers) of 8.932 mW. The designed SRAM has been fabricated through the National Chip Implementation Center (CIC), Taiwan, R.O.C.. |
