超大型積體電路蓬勃發展，電路的效能及速度也隨著製程技術的精進而提升，且目前的晶片皆趨向整合成單晶片系統(System-on-Chip)，所以在整合系統中各個子電路區塊常會出現操作的時脈相位不同，所導致之輸出資料錯誤，因此需要鎖相迴路(PLL)來減少相位偏差，使得整合系統中各個子電路的時脈相位一致，減低輸出的資料錯誤。 本論文提出之具快速鎖定之自我校正鎖相迴路，可產生具有低抖動之2.5GHz八個相位的頻率。在電路中使用多頻段之電壓控制振盪器來降低其增益KVCO，達到輸出訊號低抖動的效果，並使用自我校正的機制，讓電路在不同製程和溫度變化下，皆能鎖定在2.5GHz的頻率。自我校正電路大致上可分為開迴路校正(open-loop calibration)與閉迴路校正(close-loop calibration)兩種方法 [1]。因為上述的兩種校正方法鎖定時間較長，為了讓電路達到快速鎖定之目的，採用閉迴路校正的方法，並將此校正方法中之數位控制方式做改良。 本論文以CMOS 90nm 1P9M製程來實現，電路的工作電壓為1V。鎖相迴路的輸入參考頻率為312.5MHz，輸出頻率鎖定在2.5GHz，鎖定時輸出時脈抖動量為1.83ps(pk-pk)。若在電路的輸入參考頻率312.5MHz訊號中加入20ps(pk-pk)之時脈抖動，其輸出時脈抖動量為22.1ps(pk-pk)，鎖定時間在450ns其消耗功率為26mW。含I/O pad的晶片總面積為0.98mm^2，核心電路部份面積為0.09mm^2 The performance and speed of VLSI circuits grew up with scale-down process, and now the chip changes to integrate SOC. There is often phase error or clock skew which generate asynchronous phenomenon in different sub-circuit blocks. The different phase of operate clock that caused to output data error in integrate system. Hence, it needs Phase-Locked Loop (PLL) for decreasing phase error that make the clock phase is corresponding in order to decrease output data error in sub-circuit of integrate system. In this thesis, a fast locking self-calibration PLL is proposed. It can produce 2.5GHz output frequency and eight different phases. Multi-band scheme can decrease the gain (Kvco) of voltage controlled oscillator. That can achieve the low jitter of output signal in the PLL circuit. Self-calibration technology is used to lock the frequency of 2.5GHz at any process variation. Generally speaking, there are two kinds of self-calibration, the open-loop calibration and the close-loop calibration. However, those self-calibration methods spend the long time for frequency locked. In order to achieve the fast locking in the close-loop calibration circuit, the digital control skill of calibration method is used to improve the locking time. We use the CMOS 90nm 1P9M process with supplying 1V voltage in proposed PLL. The reference input frequency is 312.5MHz and the output frequency is 2.5GHz. The period jitter of output frequency is 1.83ps (pk-pk) .If the input signal of the PLL had 20ps jitter (pk-pk), the period jitter of output frequency was 22.1ps (pk-pk).The power consumption of the proposed PLL is 26mW at 2.5GHz and the Locking time of the PLL is 450ns. The core area is 0.09mm^2.
