三元內容定址記憶體(TCAM)在數位系統中被廣泛的使用，尤其是網路應用。可提供平行比對的功能，不過，TCAM擁有複雜的功能。此複雜的功能導致TCAM變成一個面積消耗及功率消耗的元件。因此，面積小及低功率是兩項重要的挑戰在設計一個具有成本效益的TCAM中。並且，良率改善的技術是非常重要對於TCAM而言，因為TCAM的面積通常是非常大的。 本篇論文，我們提出一個低功率TCAM使用混合樹狀NAND/NOR命中線(Hybrid Tree-NAND/NOR match line)。混合樹狀NAND/NOR的架構可以增加NAND部分的位元數目在一排TCAM中，此排造成的比較功率及比較延遲可藉由NAND部份的數目增加而減少到最低限度。因此，提出TCAM使用混合樹狀NAND/NOR命中線的比較操作的能量是非常低。我們已實現一個32x64位元的TCAM使用混合樹狀NAND/NOR命中線。此測試晶片的測量結果顯示TCAM的功率消耗只有0.4122mW在110MHz。並且，能量消耗是非常低的，只有約1.90fJ/bit/search。相比之下，與現有在一般應用中的TCAMs，被提出來的TCAM能達到較佳的能量消耗。 我們還提出一個內建自我修復(BISR)電路關於TCAM的。在BISR電路中，一個可編程序的內建自我測試(BIST)電路被提出來測量TCAM的功能缺陷和一種新的重置機制被提出來對調缺陷的元件。不同於被廣泛使用的轉換多餘(shift redundancy)電路，提出的多餘重置電路帶來固定的延遲損失不管實現多餘電路的數目。實驗結果顯示BISR電路的延遲和面積成本分別都只大約0.85ns和21920um^2。 Ternary content addressable memory (TCAM) is widely used in digital systems, especially for network applications. To support parallel comparison function, however, a TCAM has complex function. The complex function causes that the TCAM becomes an area-consuming and power-consumption component. Therefore, low-area and low-power are two major challenges in designing a cost-efficient TCAM. Also, yield improvement techniques are very important for the TCAM since the area of TCAM is usually very large. In this thesis, we propose a low-power TCAM with hybrid tree-NAND/NOR match line. The hybrid tree-NAND/NOR structure can increase the number of bits of NAND-type cells in a TCAM word such that the compare power of the word and the compare delay caused by the NAND-type cells can be minimized. Therefore, the energy of compare operation of the proposed TCAM with hybrid NAND/NOR match lines is very low. We have implemented a 32x64-bit TCAM with hybrid NAND/NOR match lines. Measurement results of the TCAM test chip show that the power consumption of the TCAM is only about 0.4122mW at 110MHz. Also, the energy consumption is very low, which is only about 1.90fJ/bit/search. In comparison with the existing TCAMs for general applications, the proposed TCAM achieve better energy consumption. We also propose a built-in self-repair (BISR) scheme for the TCAM. In the BISR scheme, a programmable built-in self-test circuit is proposed to test the functional faults of the TCAM and a novel reconfiguration mechanism is proposed to swap defective elements. Differing from the widely-used shift redundancy scheme, the proposed redundancy reconfiguration scheme incurs constant delay penalty regardless of the number of implemented redundancies. Experimental results show that the delay and the area cost of the BISR circuit are only about 0.85ns and 21920um^2, respectively.
