隨著CMOS製程技術的進步，記憶體的複雜度及時脈訊號頻率均迅速增加，因此，系統內部同步時脈訊號之可靠度便愈來愈重要。如何消除時脈偏移(Clock Skew)的問題，將成為重要的議題。 本論文實現一個應用在雙通道兩次同步動態隨機存取記憶體（Double-Data-Rate Two Synchronous Dynamic Random Access Memory, DDR2 SDRAM）中之多相位（Multiphase）輸出數位延遲鎖定迴路（Digital Delay-Locked Loop, DDLL），利用數位編碼方式，控制延遲線中不同大小的MOS電容，產生不同的延遲訊號，達成延遲時間之粗調與細調的功能，以改進整體的鎖定時間、解析度與靜態相位誤差。且電路在鎖定後，能有效地在一個週期內產生八個平均相位輸出，故亦可應用於時脈倍頻器（Frequency Multiplier）或時脈資料復原（Clock Data Recovery, CDR）電路中。 本論文之DDLL架構中分為數位控制延遲線（Digital Control Delay Line, DCDL）、相位偵測器（Phase Detector, PD）、控制單元（Control Unit, CU）、上下數計數器(Up/Dn Counter)、編碼電路(Decoder)和資料取樣電路（Data Sample Circuit, DQS）等六個部分。在粗調延遲線中一開始初始在最小的延遲，來消除Harmonic Locking的現象，並利用單一方向性的操作，來避免Stuck Locking的方法，其操作範圍為（T/2?T）之間，符合兩倍操作頻率範圍。此數位延遲鎖定迴路是利用CMOS 0.13µm 1P8M之製程來實現，電路操作電壓為1.2V在製程為TT模式下溫度40℃時，工作頻率200MHz~410MHz，鎖定時間約在18個輸入週期內鎖定。其晶片的面積為830×640µm^2 (核心面積: 463×147µm^2, 0.065mm^2)，操作在頻率為410MHz時，其峰對峰值時脈抖動量（Peak-to-Peak Jitter）為7.8ps，功率消秏為3.5mW。 To court high-frequency generation is coming with the evolution of CMOS process technology. The complexity and higher clock signal frequency of memory are increasing day after day. Therefore, the reliability of the clock signal in synchronous system becomes more and more important. How to reduce clock skew will be the most important topic of the clock synchronization circuit. This thesis describes the digital delay lock loop（DDLL）with multiphase outputs that uses the decoder technique to produce various digital code to change the delay time of delay line. In order to improve the resolution and the locking time, it also uses MOS capacitance to achieve the circuits of coarse tune and fine tune. The DDLL with multiphase outputs for double-data-rate two synchronous dynamic random access memory（DDR2 SDRAM）application can eliminate clock skew of memory. Moreover, the DDLL with multiphase outputs can be used in frequency multiplier and clock data recovery（CDR）applications. The proposed DDLL in this thesis is composed of the Digital Control Delay Line（DCDL）、Phase Detector（PD）、Control Unit（CU）、up/dn counter、decoder circuit and data sample circuit（DQS）. The initial delay of the coarse tune delay line is minimum delay time to eliminate the Harmonic Locking issue, and then it use single for direction to avoid Stuck Locking method. The operating range is (T/2?T) and accord with twice of the operating frequency range. This DDLL is implemented in a 0.13µm CMOS technology that can operate from 200 to 410MHz and the maximum lock time is 18 input clock cycles. The chip area is 830×640µm^2 with 463×147µm^2 core area.The peak-to-peak Jitter and power consumption at 410MHz are 7.8ps and 3.5mW, respectively.
