隨著CMOS製程技術的進步，追求高頻時代也來臨了。以往都是使用鎖相迴路來當作系統中晶片之間的同步電路。但是鎖相迴路的電壓控制振盪器會有抖動累積問題。因此在這邊我們使用延遲鎖定迴路與頻率倍頻器來達到所需的高頻訊號。 本論文實現了一個以寬頻操作為基礎之靜態相位誤差校正延遲鎖定迴路，其中寬頻操作是使用多頻段電壓控制延遲線來完成，多頻段電壓控制延遲線是修改餓電流式延遲線並利用頻率偵測器偵測輸入頻率來切換頻段。 在靜態相位誤差校正方面，因為相位偵測器的相位偵測死帶(dead zone)與充放電幫浦的充放電不匹配(current mismatch)以及其它非理想效應會在延遲鎖定迴路鎖定時產生靜態相位誤差，此誤差會使得頻率倍頻器的抖動效能變差。在此篇論文提出的具偵測視窗之相位偵測器(Detect Window Phase Detector)可以用來校正靜態相位誤差。延遲鎖定迴路有鎖定範圍問題，也就是電壓控制延遲線之延遲時間必須在輸入時脈週期的0.5倍與1.5倍之間，否則會發生鎖定錯誤的狀況。因此在這裡也使用了一個自我校正電路來偵測電壓控制延遲線的訊號延遲多寡並防止鎖定錯誤的問題發生。 寬頻操作為基礎之靜態相位誤差校正延遲鎖定迴路是以CMOS 0.18um 1P6M製程進行設計跟模擬，電路操作電壓為1.8V，其輸出頻率範圍為25MHz~2.5GHz。而延遲鎖定迴路之輸入頻率範圍為25MHz~250MHz，輸入頻率在250MHz時鎖定時間為253ns，最大相位誤差校正改善前為3.57°，改善後為1.098°，消耗功率為10.1mW，此時輸出頻率為2.5GHz，峰對峰值的抖動量為22.6ps，晶片面積為0.466mm^2。 To court high-frequency generation is coming with the evolution of CMOS process technology. The Phase-Locked Loop (PLL) was used for synchronous circuit between the system chips in the past. However, the voltage control oscillator have jitter accumulation problem in the PLL. Hence, Delay-Locked Loop (DLL) and frequency multiplier used to achieve the high frequency signal synchronization. DLL with static phase error calibration based on wide-range operation is proposed in this thesis. The wide-range operation is achieved in multi-band voltage controlled delay line . The multi-band voltage controlled delay line is modified current-starved delay line. It utilizes frequency detector that detect the input frequency to switch the delay line band. Due to dead zone of the phase detector, current mismatch of the charge pump and other non-ideally effect will cause the static phase error. The jitter performance of frequency multiplier will be worse. In order to solve the problems , the detect window phase detector is presented in thesis that is used to calibrate static phase error. DLL has a problem of locking range that is the delay time of voltage controlled delay line must between 0.5 times to 1.5 times for input clock period or it will occur the locking fault problem. Hence, we using a self-correct circuit to detect how long the delay time of the signal of voltage controlled delay line is. It also avoid the problem of locking fault. The proposed DLL with static phase error calibration is designed in CMOS 0.18um 1P6M process. The circuit is operate at 1.8V and the input frequency range is 25MHz~250MHz. Output frequency range is 25MHz~2.5GHz. The locking time is 253ns when the input frequency is 250MHz. Without the calibration, max phase error calibration of the proposed circuit is 3.57° and after the calibration is 1.098°.The power consumption is 10.1mW. The ten times output frequency is 2.5GHz and peak to peak jitter is 22.6ps. The core area of the chip is 0.466mm^2。
