數位電視廣播(DVB-T)在台灣將成為未來無線電視的標準規格。因此，未來對數位電視接收機的需求必將大增。本論文針對DVB-T的標準設計一基頻內接收機。內接收機所要考慮的問題有符碼邊界偏移、載波頻率偏移和取樣時脈偏移等同步問題。除此之外還有通道效應的估測和資料回復的等化問題。在本論文中將一一提出上述問題的解決方法，並提出結合載波同步與等化雙迴路架構的演算法同時解決剩餘載波頻率偏移和通道等化的問題。最後設計硬體架構實現各個演算法電路，和傳統的演算法相比可提升系統效能並節省60%的記憶體。 The European terrestrial broadcasting standard DVB-T has been adopted an official digital TV specification in Taiwan. As a result, the demand for DVB-T receiver will be heightened in the future. In this thesis, we will propose a joint carrier synchronization and equalization algorithm and implement hardware architecture for DVB-T baseband inner receiver. The OFDM inner receiver design should take account of synchronization issue, such as symbol boundary, carrier frequency offset and sampling frequency offset. In addition, the design must also take channel estimation and equalization issues into account. The proposed joint carrier synchronization and equalization algorithm can compensate both carrier frequency offset and channel frequency response at the same time. Finally, we will design the hardware architectures to realize the proposed algorithms. Comparing with the traditional methods, the proposed algorithm can promote the system performance and reduce above 60% storages.
