因應現今電路設計架構愈趨龐大與複雜，加上製程尺寸的進步。現今晶片(Chip)的電壓源供應從過去的2.5伏特，1.8伏特降低至0.13μm製程參數的1.2伏特。不出多久，小於1伏特的電壓源供應也將出現。在這樣的設計環境中，電源線上的電壓降雜訊(IR-drop)因為相對尺寸的關係，所占的比重也更為突顯。因此，電源線上的分析成為了現今電路設計中的一個相當重要課題。然而，電源線上的雜訊往往到了電路合成後的電晶體(Transistor)層級、甚至實體(Physical)層級才能被分析出來，若有不理想的情況發生，必須耗費相當多的時間才可能改進。 本篇研究的主題為提供一個區塊階層電源線上電壓降的估測模型，以便在設計初期時，可以比較方便的進行電壓降雜訊的分析。我們從高階層電流模型出發，這種電流模型的研究是已經被實現的，只要有電源線上的理想電流波形，再結合此篇研究提出的換算方法，即可估測出加入非理想電源線上電阻後的電源線上電壓變化。對設計者來說，這是一個非常方便的早期驗證方法。 With the advance of semiconductor process, the supply voltage of a chip has been shrunk to 1.2v, even less than 1v. In such designs, I-R drop noise on power lines becomes more serious due to it’s increasing ratio. Therefore, power noise analysis has become one of the most important issues in modern design flow. However, traditional power noise analysis can be performed at transistor level only, even at physical level. If power noise problems occur at such a late stage, the redesign cost is very expensive In this thesis, we propose a high-level IR-drop estimation technique to analyze supply noise at early design stages. Since high-level current waveform modeling has been developed, we propose a transformation process to translate the ideal current waveform into the current waveform with IR-drop effects. Then, the voltage drop on power lines can be obtained very quickly from the none-ideal current waveform. Therefore, this could be a convenient early verification approach for designers to estimate the IR-drop of power lines.
