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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/10293

    Title: 符合低功率與高吞吐量考慮的自適應可變長度解碼器架構設計;Architecture Design of CAVLC Decoder with Low Power and High Throughput Considerations
    Authors: 方得龍;Te-Lung Fang
    Contributors: 電機工程研究所
    Keywords: 熵解碼;平行架構;低功率考量;H.264 decoder;CAVLC decoder;multi-symbol;low power consideration
    Date: 2008-07-08
    Issue Date: 2009-09-22 12:11:05 (UTC+8)
    Publisher: 國立中央大學圖書館
    Abstract: 熵解碼器在MPEG-4 AVC/H.264基線標準中採用的是自適應可變長度解碼器。因為資料相依性的原因,傳統的自適應可變長度解碼器在解碼時會消耗大量的時脈週期、降低解碼器的效能。透過分析子模組的運算量與編碼規則,我們發現其中兩個係數的解碼運算會耗費將近百分之八十的運算時間,分別是非零係數(Level)與非零係數前零的數目(Run_before)。因此,此篇論文提出一套適用於Run_before解碼器的快速演算法和Level解碼器的平行架構設計,大量地提升了解碼的效率。根據這兩種方法的特色,我們分別稱為MLD(Multiple Level Decoding)和NZS(Non-Zero Skipping for run_before decoding)。首先,使用平行處理的架構設計非零係數(Level)解碼器,MLD的方法可以在大部分的情況下以一個時脈週期解出兩個係數(Level),而NZS方法更可以達到在同一時脈週期內產生多組係數(Run_before)。這兩種方法各自具有規則性和低複雜度設計的優點。根據比較的結果,一個Macroblock的解碼,我們的設計所需要的運算時脈最少,平均只有137個時脈週期。而估算的結果顯示,我們設計的自適應可變長度解碼器在操作頻率33.5MHz的條件下就可以達到解析度1920×1088及每秒30張的H.264影像解碼需求。相較於之前的自適應可變長度解碼器設計,此電路可以降低操作頻率約29.1% ~ 71.5%,便可達到相同規格的需求,同時合成的結果也顯示在邏輯閘的個數上並無明顯的增加。藉由降低操作頻率這樣的方式,此設計將適用於多數低功率消耗的應用。最後我們使用TSMC 0.18um標準元件庫做電路合成,將設計付諸實現成硬體。合成結果顯示,在125MHz的時脈頻率限制下,電路使用了13189個邏輯閘,而且最高操作頻率可達160MHz。 在研究期間我們也彙整了相關的研究成果並投稿2007年的IEEE亞洲固態電路會議,同年該論文於韓國濟洲發表。論文題目名稱為A Novel Design of CAVLC Decoder with Low Power Consideration,論文編號為P1236。 The entropy decoder in MPEG-4 AVC/H.264 baseline standard adopts Content Adaptive Variable Length Decoder (CAVLD). Because of symbol-to-symbol dependency, a traditional CAVLC decoder consumes lots of clock cycles in decoding and brings down the performance. We discover the decoding of two parameters spending almost eighty percent of computing time through profiling the computation of sub-modules and analyzing the encoding rules, which are non-zero coefficient (Level) and run_before. Thus this paper proposes a fast algorithm adapted for run_before decoder and the parallel architecture for level decoder, to improve the decoding performance. According to the features of these two methods, we name these two new methods as MLD (Multiple Level Decoding) and NZS (Non-Zero Skipping for run_before decoding). By performing parallel operation on level decoder, MLD can decode two levels in one cycle at most situations, and NZS can produce several values of run_before in the same cycle. These two methods have the advantages of low complexity and regularity design. According to the result of evaluation, our design needs least cycle time, 137 cycles in average, for one macroblock decoding. Moreover, the proposed CAVLC decoder can run at 33.5 MHz to meet the real time requirement for H.264 video decoding on 1920×1088 resolution. Compared with the previous designs, it can reduce around 29.1% to 71.5% on operation frequency for the same requirement, but even no increase on the gate count. With an aid on a lower operation frequency, it will be suitable for many low power applications. Our proposed design has been implemented and synthesized with TSMC 0.18um Standard Cell Library. The synthesis result shows that the gate count is 13189 gates with the clock constraint of 125 MHz, and the maximum frequency is up to 160 MHz.
    Appears in Collections:[電機工程研究所] 博碩士論文

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