由於近年環保意識的提升，加上可攜式無線通訊電子產品需求量的增加，因此在電路設計上，為了達到節約能源並延長電池壽命的目的，最簡單且直接的做法便是降低操作電壓。而且為了減少手持式電子產品上電池系統所佔的體積及重量，太陽能電池是目前最符合需求的低汙染能源，不但能減少發電過程中溫室效應氣體的排放，而且在光照充足的地區就能得到持續的供電，而一個太陽能電池所能供應的電壓約只有0.5-V，因此我們設計了一個能操作在供應電壓為0.5-V的鎖相迴路。 鎖相迴路是通訊系統中用來產生同步時脈的重要電路之一，因此也不能忽略鎖相迴路的功率消耗。在本論文中提出的鎖相迴路可以操作在0.5-V的低電壓，並輸出1.25-GHz八個相位的頻率，以達到高頻低功率的目的。此鎖相迴路使用改良式的閘極控制充放電幫浦，其不但能在低電壓下操作，並且能抑制傳統閘極控制充放電幫浦的漏電流。電壓控制振盪器部分使用多頻帶式基極驅動電壓控制振盪器，多頻帶的設計可降低其KVCO以減少電壓雜訊對輸出抖動的影響，且鎖相迴路可以在製程、電壓及溫度變異下仍鎖定在1.25-GHz的輸出頻率，此外基極驅動式的電壓控制振盪器比起傳統架構的電壓控制振盪器擁有較佳的線性度。本晶片以UMC 90nm 1P9M standard CMOS with RVT devices製程實現，當輸出頻率為1.25-GHz時，功率消耗為1.59 mW，其輸出的抖動為33.33 ps (p-p)，晶片的核心部分面積為0.074 mm2。 In recent years, environmental protect issue has became more and more important. With the requirement on the portable wireless communication equipment increasing, the supply voltage should be downscaled to reduce power consumption and increase the lifetime of batteries. To reduce the cumbersome battery system and save energy, solar cell is popular green energy source and useful for supplying energy in portable electric products. Because that the voltage of a solar cell supplying is about 0.5V, we design a PLL with 0.5-V supply voltage. Being a major block in a communication system, the power consumption of the PLL is not able to neglect. A 0.5-V 1.25-GHz 8-phase phase-locked loop (PLL) is proposed to achieve high output frequency and low power consumption. The proposed charge pump (CP) circuit has advantage of operating at low supply voltage and reducing the leakage current. The proposed bulk-driven voltage control oscillator (VCO) with digital-to-analog converter has advantage of operating at low supply voltage with using the bulk-controlled technique. The VCO use multi-band technique to degrade the KVCO, so that the noise effect would be reduced. Moreover, the VCO can lock at 1.25GHz output frequency with the process, voltage, and temperature (PVT) variation. The delay cell of VCO has higher linearity than the conventional delay cell by using bulk-controlled technique. The test chip is implemented in UMC 90nm 1P9M standard CMOS with RVT devices process. The output jitter performance of the proposed PLL is 33.33 ps (p-p) at 1.25- GHz. The power consumption of the PLL is 1.59 mW at 1.25-GHz and the core area is 0.074 mm2.
