隨著製程的進步，越來越多的電晶體被整合至單一晶片內。晶片設計者趨向於使用有規律架構之傳輸網路來解決複雜晶片在效能、能量消耗以及可靠度等方面所遭遇的瓶頸。網路晶片是一種新的傳輸架構，目前被廣泛的運用於大尺度的晶片中。而記憶體也是最常被使用於複雜晶片中的組件。 在本篇論文中，我們提出了一種運用封包的自我測試電路以及自我修復電路，該電路可以針對網狀架構之網路晶片上的隨機存取記憶體進行測試以及修復動作。自我測試與自我修復電路可以重複利用網路晶片上的網路架構去傳輸測試圖騰，當自我測試與自我修復電路對大量記憶體進行測試及修復時，不會受到繞線問題的限制。因此，可以大幅度的降低自我測試以及自我修復電路的額外面積消耗。而我們所提出的自我測試和修復電路更能夠降低整體測試時間並且提高晶片的良率。由實驗數據可以看出，我們所提出運用封包的自我測試和自我修復電路用於測試十五個8Kx64-bit的記憶體時，其所需增加的面積分別為百分之零點九二和百分之一點三八。而且，自我修復電路可以有效地提高晶片良率。舉例來說：『可以將十五個8Kx64-bit記憶體組成的晶片良率由百分之八十提升至百分之九十四。』 With the advent CMOS technology, more and more transistors can be integrated in a single chip. To cope with the bottleneck of performance, power, reliability, etc. of a complicated chip, the chip designer tends to design the chip using a regular architecture with on-chip communication network. Network-on-Chip (NoC) is one popular on-chip communication approach for large-scale chips. Also, memory core usually is the most used component in such complex chips. This thesis proposes a packet-based built-in self-test (BIST) scheme and a packet-based built-in self-repair (BISR) scheme for testing and repairing random access memories (RAMs) in mesh-based NoCs. The BIST and BISR schemes reuse the NoC to transport test patterns such that the number of RAMs tested and repaired by the BIST and BISR circuits are not limited by the routing issue. Therefore, the area overhead of the BIST and BISR circuits can be drastically reduced. Moreover, the proposed BIST and BISR schemes can reduce the memory test time and increase the yield of the chip. Experimental results show that the area overhead of the packet-based BIST circuit and the packet-based BISR circuit is only about 0.92% and 1.38% for fifteen 8Kx64-bit RAMs, respectively. Also, the BISR scheme can efficiently boost the yield of the chip. For example, the yield of fifteen 8Kx64-bit RAMs can be boosted from 80% to 94%.
