製作於砷化鎵基板之BiFET(Bipolar/FET)元件特性及其微波電路應用; Bi-FET (Bipolar/FET) Device Characteristics and Microwave Circuit Applications

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/10317

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/10317

Title:	製作於砷化鎵基板之BiFET(Bipolar/FET)元件特性及其微波電路應用;Bi-FET (Bipolar/FET) Device Characteristics and Microwave Circuit Applications
Authors:	沈稚鈞;Chih-Chun Shen
Contributors:	電機工程研究所
Keywords:	異質接面雙載子電晶體;切換開關;假晶格高電子遷移率場效應電晶體;砷化鎵;功率放大器;switch;power amplifier;pHEMT;HBT;Bi-FET
Date:	2008-06-30
Issue Date:	2009-09-22 12:12:04 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	此論文研究的內容主要有兩個部份，一是Bi-FET元件特性探討，元件包括了假晶格高電子遷移率場效電晶體(pHEMTs)及異質接面雙極性電晶體(HBTs)，並利用此製程設計了同時使用pHEMTs與HBTs的整合電路；另一是堆疊式功率放大器(Stacked Power Amplifier)設計，將電晶體利用串聯方式來提升直流電壓，藉此得到較大的輸出功率。元件特性部分有直流特性與高頻特性，並與一般GaAs基板的元件做比較，且分別萃取元件的小訊號等效模型加以分析，並特別針對兩種不同基板的HBTs大訊號特性做比較。整合電路方面主要為功率放大器配合切換開關，功率放大器使用HBTs設計，切換開關使用pHEMTs設計，設計的電路可分為兩種：一為利用在放大器輸出端的匹配網路上加上一個切換式開關作為高功率以及低功率模態的轉換，藉此能同時在高功率與低功率模態操作時都能達到阻抗匹配，其設計頻率為2 GHz；二為將功率放大器配合上SPDT的切換開關，應用於收發機輸出端模組，功率放大器方面則使用堆疊方式來設計，以共射極(Common-Emitter)架構與共基極(Common-Base)架構電晶體組成，本論文提出共基極之基極端的電容值設計方式，並以Bi-FET製程驗證電路特性，設計頻率為5 GHz。 In this thesis, there are two key parts. One is the Bi-FET device characteristics, including pHEMT devices and HBT devices. The two devices are both available in this process. The other is design of power amplifier using a stacked topology. To get higher output power by higher voltage, the transistors are connected in series. The characteristics of Bi-FET devices, including dc and RF performances are compared with other standard processes with GaAs substrate. Large signal characteristics were for HBT between two different substrates. For the integrated circuit, HBT device was designed for power amplifier, and pHEMT device was designed for switch. One of the two integrated circuits was proposed using a D-mode pHEMT switch to achieve high efficiency for both high and low output power modes. The circuit was designed at 2 GHz. The other was to integrate the power amplifier with a SPDT switch for the output of the transceiver. The power amplifier was designed using a stacked topology, include of common-emitter and common-base configuration transistors. The capacitance of the capacitor at the base of the common-base transistor was derived in the thesis. The circuit was designed using Bi-FET process at 5 GHz and 2 GHz adaptive power amplifier.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Size	Format

社群 sharing

Loading...