應用在SATA-III上6Gbps展頻時脈產生器; A 6Gbps SATA-III Spread Spectrum Clock Generator

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/10392

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題名:	應用在SATA-III上6Gbps展頻時脈產生器;A 6Gbps SATA-III Spread Spectrum Clock Generator
作者:	張誌顯;Chih-Hsien Chang
貢獻者:	電機工程研究所
關鍵詞:	非整數頻率除頻器;展頻時脈產生器;Fractional-N PLL;SATA;Spread Spectrum Clock Generator
日期:	2008-10-29
上傳時間:	2009-09-22 12:15:08 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	近年來電腦串列資料傳輸介面(Serial-ATA)其速度已高達到數每秒數億個位元。在時脈頻率的提高其因為電子充放電所造成的電磁干擾效應(EMI)越來越嚴重，其電磁干擾將會是介面傳輸系統中最主要雜訊的來源，因此時脈產生器在Serial-ATA系統中扮演越來越重要的角色。為了降低電磁干擾效應會有一些技術已被提出：如屏蔽技術是依重非常傳統並有效的技術，但利用此技術將會增加重量與面積不適用在可攜式產品中；而另一種技術是利用時脈展頻的技術，經由頻率調變將中心頻率向下展開5000ppm的量，而此技術可有效壓抑電磁干擾效應並較屏蔽效應可程式化，且在有限的增加晶片面積。最後本論文提出一新式的展頻時脈產生器電路，並透過晶片量測來驗證電路可行性。本論文利用相位內插器與多模數頻率除頻器提出一個新式的非整數頻率除頻器，最後利用依基本的鎖相迴路與新式的非整數除頻器來完成一個可以應用在Serial-ATA III上之6 Gbps展頻時脈產生器。展頻時脈產生器利用聯電 0.09μm標準CMOS製程圞成中心操作頻率為6 Gbps並向下展開5000 ppm且利用一個頻率31.3 KHz三角波來調變頻率。在6 GHz未展頻的情況下峰對峰抖動(peak-to-peak Jitter)為8.17 ps，具有5.97~6.0 GHz展頻的情況下峰對峰抖動(peak-to-peak Jitter)為9.05 ps，在展頻的電磁干擾的壓抑約為18.83 dB。在1.0 V電壓操作下功率消耗為27.69 mW，整體晶片面積為0.85×0.85mm2。 A Serial AT Attachment (SATA) has been a popular communication in today’s computer system. As SATA transmission rate is up to multi-gigabits per second. The clock generator is becoming an important component in high speed communication system. As the clock frequency becomes faster, the electromagnetic interference (EMI) induced by the clock generator will effect the other equipments. It will be the major noise source in SATA system which becomes an important design issue. Reducing EMI has several methods. Shield cables and coaxial wires are conventional to reduce EMI method, but there is generally costly and bulky. The popular to reduce EMI method at present is spread spectrum clock generator (SSCG), based on a frequency modulation, that altering the center frequency. SSCG can reduce EMI to the goal of low-cost and flexibility. A 6 Gbps Spread Spectrum Clock Generator (SSCG) for Serial-ATA III is realized in this thesis by a new fractional-N phase-locked loop. The fractional-N division is implemented by a dual-modulus divide and a phase interpolator (PI). The SSCG achieves an output clock of 6 Gbps and 5000ppm down spread with a 31.3 KHz triangular waveform and been designed based on UMC 0.09μm 1p9m CMOS process. The peak-to-peak jitter of non spread-spectrum clock is 8.17ps, and the peak-to-peak jitter of spread-spectrum clock is 9.05ps. The EMI reduction is 18.83dB with normal frequency spread modulation from 6GHz to 5.97GHz. The chip area is 890μm × 890μm. The power is 27.69 mW under 1.0-V supply voltage.
顯示於類別:	[電機工程研究所] 博碩士論文

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