應用於Ka頻帶之移相器及壓控振盪器暨Ka/V頻帶低雜訊放大器之研製; mplementation of Ka-band Phase Shifter, VCO, and Ka/V-band LNA Circuits

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Title:	應用於Ka頻帶之移相器及壓控振盪器暨Ka/V頻帶低雜訊放大器之研製;mplementation of Ka-band Phase Shifter, VCO, and Ka/V-band LNA Circuits
Authors:	李冠融;Kuan-zung Lee
Contributors:	電機工程研究所
Keywords:	低雜訊放大器;移相器;壓控振盪器;VCO;Phase Shifter;LNA
Date:	2009-07-06
Issue Date:	2009-09-22 12:15:20 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	本論文係以TSMC 0.18?m CMOS 製程，TSMC 0.13?m CMOS 製程以及UMC 0.09?m CMOS 製程來完成相位陣列接收機的幾個電路。主要設計的電路為移相器、可變增益放大器、低雜訊放大器以及壓控振盪器。第一部分為移相器以及可變增益放大器之研製。反射式移相器是由一個3-dB耦合器加上兩個反射式負載所達成，量測到的結果可調相移量為155°，插入損耗為10.9 ± 2.2 dB，輸入及輸出返回損耗都小於-17dB，本電路無功率消耗，另外晶片面積為 0.403 mm2。可變增益放大器由三級的放大器所組成，量測到的結果增益在28.2GHz為17.27dB，可調增益範圍為23dB，優化指標經換算為66.55 GHz/mW，另外晶片面積為0.49 mm2。第二部分為低雜訊放大器之研製。使用電流再利用低雜訊放大器是將兩級共源級放大器疊接以達到節省一路電流的利用，量測到的結果增益在30.6GHz為9.02dB，3-dB頻寬為5.2GHz，雜訊指數為4.03 dB，另外晶片面積為 0.63 mm2。使用高品質短波共平面波導的來匹配的低雜訊放大器，量測到的結果增益在28.8GHz為15.79dB，3-dB頻寬為4.6GHz，雜訊指數為4.11 dB，整體功耗只需16.65mW，另外晶片面積為 0.63 mm2。用0.13-?m製程之低功耗放大器電路架構為3級共源級放大器，省略級間阻隔偏壓的電容來提升增益降低雜訊，量測到的結果增益在51.2GHz為10.6dB，3-dB頻寬為6.8GHz，雜訊指數為5.658 dB，整體功耗只需8.065mW，另外晶片面積為 0.39 mm2。最後是用0.09-?m製程之小面積低功耗放大器，匹配皆用螺旋狀電感來達到相當小的面積。量測到的結果增益在43.2GHz為14.02 dB，3-dB頻寬為5.7GHz，雜訊指數為5.18 dB，整體功耗只需11.858mW，另外晶片面積不算Pad僅僅為 0.132mm2。第三部分為壓控振盪器之研製。利用變壓器耦合達到低電壓操作。由量測結果可知，中心震盪頻率為25.49GHz,在離主頻1MHz之相位雜訊為-99.3 dBc/Hz，輸出功率為 -4.2 ~ -6.2 dBm，核心電路功率消耗為5.12 mW，而優化指標為-180.3 dBc/Hz，另外晶片面積為 0.278 mm2。 This paper investigates phased array receiver circuits implemented in TSMC 0.18-?m CMOS, 0.13-?m CMOS, and UMC 0.09-?m CMOS technologies. The implemented circuits include the phase shifter, variable gain amplifier, low noise amplifier, and voltage controlled oscillator. The first section presents the design of phase shifter and variable gain amplifier. The reflection type phase shifter uses a 3-dB quadrature coupler with two reflective loads and does not need any power consumption. The measured phase-shift range is greater than 155°, the insertion loss is 10.9 ± 2.2 dB. And return loss is better than 17dB. The chip area is 0.403 mm2. The variable gain amplifier employs cascade three-stage to achieve high gain. The peak small signal gain of 17.27 dB is obtained at 28.2 GHz. The dynamic range of gain control is 23dB. A ﬁgure-of-merit (FoM) regarding a high peak gain-frequency product per dc power is 66.55 GHz/mW. The chip area is 0.49 mm2. The second section describes the design of four low noise amplifiers. A Ka-band current reuse LNA, two cascade common source amplifiers share the same supply current to reduce dc current consumption. The peak small signal gain is 9.02 dB at 30.6 GHz, with 3-dB bandwidth of 5.2 GHz from 27.1 to 32.3 GHz. The obtained NF is less than 4.03 dB at 28GHz. The chip area is 0.63 mm2. A Ka-band using slow wave CPW lines (S-CPW) LNA for matching elements is proposed to obtain the high Q of matching networks, and thus achieves a high gain LNA. The peak small signal gain is 15.79 dB at 28.8 GHz, with 3-dB bandwidth of 4.6 GHz from 26.8 to 31.4 GHz. The obtained NF is less than 4.11 dB at 29.5GHz. The chip area is 0.73 mm2. A low power consumption V-band LNA with thin film microstrip lines matching networks was implemented in 0.13-?m CMOS technology. The peak small signal gain is 10.6 dB at 51.2 GHz with 3-dB bandwidth of 6.8 GHz from 48.4 to 55.2 GHz. The obtained NF is less than 5.658 dB at 57.5GHz. The power consumption is only 8.065 mW. The chip area is 0.39 mm2. A low power consumption with very compact lumped matching networks V-Band was implemented in 0.09-?m CMOS technology. The small signal gain has a peak of 14.02 dB at 43.2 GHz, with 3-dB bandwidth of 5.7 GHz from 40.4 to 46.1 GHz. The obtained NF is less than 5.18dB at 42.5GHz. The power consumption is 11.858 mW and the chip area without pad is 0.132 mm2 The third section presents a transformer feedback VCO design which is adopted to achieve low supply voltage. The measured oscillation frequency is 25.49 GHz with a phase noise of -99.3 dBc/Hz at 1 MHz offset. The output power of VCO with cable loss is -4.2~-6.2 dBm. The power consumption of VCO is 5.12 mW with a FoM of -180.3 dBc/Hz. The chip area is 0.278 mm2
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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