自動降低運算跨導放大器電路之製程變異敏感度的研究; Automatic Process Sensitivity Reduction for OTA Circuits

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題名:	自動降低運算跨導放大器電路之製程變異敏感度的研究;Automatic Process Sensitivity Reduction for OTA Circuits
作者:	傅仁弘;Ren-Hong Fu
貢獻者:	電機工程研究所
關鍵詞:	運算跨導放大器;製程變異敏感度;OTA;process variation sensitivity
日期:	2009-07-06
上傳時間:	2009-09-22 12:15:23 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	隨著製程技術的進步，製程變異對電路元件的影響也越來越大，造成設計良率不斷下降。為了解決這個問題，以設計為導向的良率改善(design-for-yield)技術是一個相當熱門的研究方向，在設計的流程中，導入製程變異對電路的影響，將製程變異對電路的影響降低。本論文提出一個自動降低電路的製程變異敏感度的方法，藉由分析電晶體(MOS)尺寸與製程變異敏感度之間的關係，來對運算跨導放大器(operational transconductance amplifier, OTA)電路進行自動元件尺寸調整，以降低其製程變異敏感度(process variation sensitivity)。整個流程以C語言實現。在電路效能不做太大的變動的前提下，透過退火演算法(simulated annealing)，來對電路面積與製程變異敏感度做最佳化。從實驗結果觀察，本論文所提出的方法確實可以降低製程變異敏感度，進而提升設計良率。 With the advance process technology, process variation has more and more impacts on the device behaviors, which reduces the design yield dramatically. In order to solve this problem, design-for-yield (DFY) techniques are hot research topics recently. In the DFY design flow, the influence of process variation will be considered at early design stage to reduce the process variation impacts on the circuits. In this thesis, an automatic DFY approach is proposed for OTA circuits to reduce their process variation sensitivity. According to the relationship between transistor sizes and process variation sensitivity, the proposed flow automatically adjusts the transistor sizes to reduce process variation sensitivity of OTA circuits. This flow has been implemented by C language. With little changing on circuit performances, this program will find an optimal solution considering the process sensitivity and area overhead using simulated annealing algorithm. As shown in the experimental results, the proposed approach does reduce the process variation sensitivity and improve the design yield.
顯示於類別:	[電機工程研究所] 博碩士論文

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