隨著製程的演進，積體電路的尺寸已經進入奈米（nanometer）技術的時代。由於製程微縮的影響，製程變異（process variation）與良率損失（yield loss）的議題亦變的不容忽視，尤其是針對較敏感的類比電路。因此積體電路的可行性製造設計（design for manufacturability, DFM）以及以良率為導向（design for yield, DFY）的電路設計概念亦更備受重視。期望在電路設計的階段，就能將電路在實際製造過程中，可能遭受的製程變異現象考慮進來，設計出符合以良率導向為前提的電路設計，不僅能夠免去重新設計電路所需耗費的時程，在經濟效益上也有很大的提升。 本論文是以一個充電幫浦式的鎖相迴路（charge pump phase-locked loop, CPPLL）為研究實例，提出一套可以降低製程變異敏感度的電路調整流程（sensitivity reduction sizing flow），以階層式（hierarchical）的概念，將此調整策略套用在鎖相迴路中對製程變異較為敏感（sensitivity）的類比電路上，針對各電路的幾何參數進行方向性的調整，期望在標稱效能點（nominal performance）近乎維持不變的原則下，達到改善電路對製程敏感度的目的。而反應在鎖相迴路效能層面的良率亦能有不錯的提升。 Along with the evolution of manufacturing process, the size of integrated circuits has shrunk into the nanometer scale. Process variation and yield loss issues became more and more serious, especially for analog circuits. Therefore, the design-for-manufacturability (DFM) and design-for-yield (DFY) techniques have been widely used to reduce the impacts of those negative effects. If designers can consider the process variation phenomena in early design stages, the design iterations could be shortened significantly to achieve better economical benefit. In this thesis, we propose a sizing flow for the phase-locked loop circuits with a charge pump to reduce the process sensitivity. Using the hierarchical concept, the geometrical parameters of the sensitivity analog blocks are adjusted for sensitivity reduction with similar nominal performance, the yield of PLL is improved significantly after sensitivity reduction as shown in the experimental results.
