目前非揮發性記憶體在元件尺寸持續微縮的趨勢下，其需求為高密度記憶單元、低功率損耗、快速讀寫操作、以及良好的可靠度。奈米晶粒非揮發性記憶體可能取代傳統的浮動閘極記憶體，由於奈米晶粒可視為電荷存層中彼此分離的儲存點，可以有效改善小尺寸記憶體元件在多次操作後的資料儲存能力。 本論文的主題是研製以鍺奈米晶粒當作電荷儲存點的多位元密度非揮發性記憶體單胞元。首先探討製程步驟不太複雜的鍺奈米晶粒閘極堆疊層的性質，調整其製程參數使其可擁有最佳的電荷儲存效能，主要著重於大的記憶窗口、分佈均勻且密度高的鍺奈米晶粒層等特性。接著再將製程參數及效能最佳化的鍺奈米晶粒閘極堆疊應用多位元密度的非揮發性記憶體單胞元。單胞元係利用三維立體結構的設計，將電荷儲存點製作在矽洞的四側斜邊，使非揮發性記憶體單胞元擁有四個位元的儲存位置，此非揮發性記憶體單胞元製程與現階段的積體電路製程相容，所以具商業化的可能性。 Current requirements of nonvolatile memory (NVM) for the scaling down device are high density cells, low-power consumption, high-speed operation and good reliability. The nonvolatile memories with nanocrystals are one of promising candidates to substitute for the conventional floating-gate memory, because the nanocrystals discrete charge storage nodes have effectively improved the data retention under endurance test for the scaling down device. In this thesis, the multi-bit nonvolatile memory cell with Ge nanocrystals as the charge trapping nodes has been fabricated and demonstrated. Firstly, the Ge nanocrystals gate stack with rather simple fabrication process has been studied to optimize process conditions and performance (e.g. large memory window and high density Ge nanocrystals with uniform distribution, etc.). Then, the optimum Ge nanocrystals gate stack was used to fabricate the multi-bit NVM cell. The application of three-dimensional cell structure led the cell to the advantage of multi-bit capacity. The fabrication processes of this NVM cell were compatible with current IC manufacturing process. The multi-bit NVM cell studied commercialization in the feature.
