半導體產業中，最主要目的就是如何在最小的成本中發輝到最大的績效，像是減少晶圓的碰撞、避免發生晶舟或是OHT阻塞、減少晶圓的搬運距離以及週期時間等等，都會攸關到晶圓生產的績效，所以如何將績效發輝到最大就是最主要的問題。而又以廠房的規劃最為重要，如何在有限的空間做最有效的運用，如果能掌握到這一點，相信在企業上占有一席之地。 本研究的主要動機在於一般晶圓廠主要是以脊椎式為主的佈置，往往在Bay裡面加工完之後，又必須運送到最外部的Stocker才能夠再進行加工，如果可以在Bay與Bay之間設置一條相通的軌道，那麼在Bay裡面加工完成之後就能直接經由這條軌道進行運送，相信會節省不少的搬運時間。因此，如何規劃出這條軌道，使它發輝的效率最大，是個很重要的關鍵。 本研究將針對『晶圓廠內設施規劃』中的『脊椎式』做有系統的規劃與佈置：本研究和一般不同的是在於同時考慮IntraBay與InterBay的規劃，因此會先就Bay內的機台來做規劃，根據流量分析法、模擬退火法與額外增加成本來做實驗分析。而Bay之間的排列則會運用到數學模型來求解。吾人利用Visual C++來找出迴圈的排列佈置，以及CPLEX7.0進行實驗，以最小化總流量距離為目標函數。然後針對演算法作說明，進而對未來研究的建議，希望能作為晶圓廠設施佈置的參考指標。 In semiconductor manufacturing, getting high performance in low cost such as reducing work in process, delivery distance or delivery time, cycle time and increase yield is the most important purpose. How to get the high performance is the question. The facility layout design and AMHS, doing the best in finite space, are the questions to achieve a successful 300mm fab. The purpose on this paper is that the products to process of the Bay must pass through the Stocker, it is almost cost a lot of time. If we can set up a Direct Transport Track within Bays to make the products pass through without Stocker. We trust that set up a Direct Transport Track can reduce transportation distance and save a lot of time. For this reason to plan the best Direct Transport Track, we must consider the IntraBay and InterBay layout. The paper focuses on spine configuration in fab layout, and in different of other papers, it considers the IntraBay and InterBay defined. To achieve a short transportation distance both in IntraBay and InterBay, we using heuristic algorithm and mathematical model. First, we defined the machine layout of Bay by FLA method, Simulated Annealing, and Extra cost. Second, we defined the Bay layout by Visual C++ and mathematical model using CPLEX 7.0. Final, we find the Direct Transport Track also by mathematical model. Based on this analysis, we expect that the facility layout will reduce transportation distance of wafer lots, and increase equipment utility.
