應用於特殊半導體記憶體之測試與可靠性設計技術; Testing and Design-for-Reliability Techniques for Specific Semiconductor Memories

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/25797

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Title:	應用於特殊半導體記憶體之測試與可靠性設計技術;Testing and Design-for-Reliability Techniques for Specific Semiconductor Memories
Authors:	永昇平;Sheng-ping Yung
Contributors:	電機工程研究所
Keywords:	測試演算法;可靠度模型;可靠性設計;錯誤模型;記憶體測試;錯誤偵測及更正;8T靜態隨機存取記憶體;內容定址記憶體;design-for-reliability;reliability model;test algorithm;fault model;memory testing;error detection and correction (EDAC);8T-SRAM;content addressable memory
Date:	2009-09-28
Issue Date:	2010-06-11 16:20:07 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	可靠度是奈米層級(nano-scale)積體電路的重要議題之一。在積體電路裡，一個未受任何機制所保護的記憶體是相當容易遇到可靠度不足的問題。而一個典型的6T (six-transistor)靜態隨機存取記憶體(static random access memory，SRAM)因製程變異的影響，已經面臨到靜態雜訊邊際(static noise margin)嚴重縮減的問題。所以，一個利用讀寫埠分離來達到提升讀寫靜態雜訊邊際的8T(eight-transistor) 靜態隨機存取記憶體被提出來解決6T靜態隨機存取記憶體靜態雜訊邊際嚴重縮減的問題。由於8T靜態隨機存取記憶體與6T靜態隨機存取記憶體架構上的不同，一個存在於8T靜態隨機存取記憶體上的瑕疵可能會引發一個以往未曾定義在6T靜態隨機存取記憶體上的新錯誤模型。因此，在本論文的第一部分，我們定義了一些存在於8T靜態隨機存取記憶體上的新錯誤模型，並且提出了一個測試演算法來偵測這些新錯誤模型。另一方面，內容定址記憶體(content addressable memory，CAM)廣泛的使用在數位系統上。一個內容定址記憶體細胞(cell)是由一個靜態隨機存取記憶體及一個比較器所組成。所以一個內容定址記憶體也同樣會遇到靜態隨機存取記憶體靜態雜訊邊際嚴重縮減的問題。雖然許多的變異容忍靜態隨機存取記憶體已經被提出來解決此一問題，但是卻沒有任何關於變異容忍的內容定址記憶體設計被提出。所以，在本論文的第二部分，我們提出了一些變異度容忍的內容定址記憶體細胞。實驗結果顯示，這些提出來的細胞只要付出少許的面積花費，就可以擁有相當傑出的讀寫靜態雜訊邊際。此外，我們更對這些變異度容忍的細胞進行可測試度(testability)分析。而分析結果顯示，我們所提出來的變異度容忍細胞在進行比較錯誤(comparison faults)的偵測時，擁有比典型內容定址記憶體還要低的測試複雜度。所以，我們所提出來的內容定址記憶體細胞不只擁有傑出的讀寫靜態雜訊邊際，同時也可以降低比較錯誤的測試複雜度。錯誤偵測與更正(error detection and correction，EDAC)機制被廣泛使用於保護隨機存取記憶體免於遭受軟錯誤(soft errors)的侵襲。一個內容定址記憶體除了讀取與寫入的功能外，還多了一個平行比對的操作可供使用。而這個平行比對的操作使得應用於隨機存取記憶體上的錯誤偵測與更正機制無法順利移植到內容定址記憶體當中。所以，在本論文的最後部分，我們提出了兩種即時的錯誤偵測及更正機制，使其可以成功應用在內容定址記憶體上。而且實驗結果顯示，所提出的錯誤偵測及更正機制只要付出少許面積花費就可以為內容定址記憶體提供相當傑出的可靠度。 Reliability is one important issue for designing nano-scale integrated circuits. Among integrated circuits, a memory circuit without any protection mechanism is easily prone to the problem of reliability. The typical 6T-SRAM has faced the impact of the drastic reduction of static noise margin (SNM) due to the process variation. To cope with this ssue, an 8T-SRAM cell has been proposed to enhance the read and write SNM by separating the read port and write port. Since the circuit structure of an 8T-SRAM cell is different from that of a 6T-SRAM cell, a defect in an 8TSRAM cell may be manifested as a new functional fault which does not exist in a 6T-SRAM cell. In the first part of this thesis, therefore, we define new functional fault models for the 8T-SRAM cell. Also, a test algorithm for covering the defined functional faults is proposed. A content addressable memory (CAM) is also widely used in digital systems. A CAM cell consists of a SRAM cell and a comparator. Although various variability-tolerant SRAM cells have been proposed, no variability-tolerant CAM cells are reported. In the second part of this thesis, therefore, we propose several variability-tolerant CAM cells. Experimental results show that these CAM cells have good read and write SNMs with a small amount of area cost. Moreover, the testability of these variability-tolerant CAM cells has also been investigated. Analysis results show that test complexity for detecting the comparison faults of the proposed variability-tolerant CAM cells is lower than that of typical CAM cells. Error detection and correction (EDAC) scheme is widely used to protect a RAM from soft errors. However, a CAM has a parallel compare operation in addition to a read and a write operations. The parallel compare operation makes the EDAC scheme for RAMs not be able to be applied in CAMs. In the last part of thesis, therefore, two concurrent EDAC schemes for CAMs are proposed. Analysis results show that the proposed EDAC schemes can provide much better reliability for a CAM than the existing EDAC schemes.
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