以數位信號處理器實現H.264/SVC解碼器及其最佳化演算法設計; The Realization and Optimization Technique for H.264/SVC decoder on Digital Signal Processor Platform

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Title:	以數位信號處理器實現H.264/SVC解碼器及其最佳化演算法設計;The Realization and Optimization Technique for H.264/SVC decoder on Digital Signal Processor Platform
Authors:	林黃淳;Huang-Chun Lin
Contributors:	電機工程研究所
Keywords:	餘弦離散轉換;可調式解碼器;數位訊號處理器;視訊解碼器;DCT;Decoder;H.264/SVC;Digital signal processor
Date:	2009-11-24
Issue Date:	2010-06-11 16:20:35 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	隨著多媒體的應用越來越多，要使一個多媒體視訊壓縮影片符合不同的多媒體媒介，例如：車用通訊、手機影音、電腦和HD 電視等多媒體設備，則多媒體編解碼器需要更符合這些硬體配備的需求來進行視訊的編解碼，為了因應這種需求，ITU-T Video Coding Experts Group基於H.264/AVC發展了延伸於H.264編解碼標準H.264/SVC[1]， H.264/SVC 編解碼標準針對了撥放影格率、解析度、畫面品質精細度這三種不同的型態來進行可伸縮視訊編碼，編碼後的視訊位元流可以解碼成符合不同解析度、網路條件和硬體能力的多媒體設備的影片資訊。然而，這種編解碼技術其模組複雜度相當的高，而降低其複雜度在現今乃是一個非常重要的議題。本篇論文利用數位訊號處理器實現H.264/SVC解碼器，而在H.264/SVC解碼器方面是以參考軟體JSVM9.16[2]來移植於數位處理器平台DM6437[3]。我們經由計算各種不同可伸縮功能Temporal、Spatial、SNR 及Combine 模式來進行其分析，針對分析出來的結果來進行各模組的最佳化。此篇論文提出了在反離散餘弦轉換模組(Inverse discrete cosine transform)及內插放大模組(Interpolation Up-sampling)這兩個部份的基於DM6437的最佳化方法，並分別達到10.7倍和平均12.29倍的效能提升。除此之外利用開發環境的工具、記憶體的規劃及一些特殊指令來最佳化我們的H.264/SVC解碼器系統使其在Combine的模式下得到5.79 倍的效能提升。在本篇最後，會闡述一個可伸縮視訊解碼撥放器完整的系統實現在DM6437 開發平台上，此系統利用網路由電腦傳輸壓縮過的視訊位元流將其傳送到DM6437 開發板進行資料的解壓縮，解壓縮過後的資料並以液晶螢幕顯示出來，在可伸縮的功能實現上，我們利用開發平台的指撥開關來調整Temporal、Spatial、SNR 和Combine 等模式，而此功能的實現還需嵌入一個位元流擷取器(Bitstream Extractor)方得實現。 The video coding technique has been extensively applied in many scenarios of our daily life. For example: vehicle electronics applications, mobile phone, computer, high-definition television ...etc. To support such various applications, a versatile video coding scheme is essential. Therefore, ITU-T Video Coding Experts Group has developed a video standard H.264/SVC [1], an extension of H.264/AVC [7]. It can provide the bitstream adaption to fit in with different resolution, network condition and hardware capability. The H.264/SVC includes three types of scalability: temporal, spatial and SNR scalability. However, the complexity of H.264/SVC decoder is very high. For this reason, how to reduce the complexity of H.264/SVC is very important issue. In this thesis, we realize the H.264/SVC decoder with Texas Instrument DM6437 DSP platform. This work transplants the reference software JSVM9.16 [2] to the DSP platform DM6437 [3]. We separately analyze the complexity of H.264/SVC decoder in for temporal, spatial, SNR and Combine scalability. According to the analysis result, we optimize each module of H.264/SVC decoder. This thesis proposed two optimization methodologies in inverse discrete cosine transform (IDCT) module and up-sampling module. With both optimizations, the performance of IDCT and up sampling module can be increased as high as 10.7x and 12.29x, respectively. Besides, we also utilized the Code Composer Studio (CCS) to draw up the memory mapping and explored some special intrinsic instructions to improve the decoding performance. The overall decoder system can speed up 5.79x on average. Finally, we will show a complete H.264/SVC decoder system. It is implemented in DM6437 DSK. This system received the bitstream through network and decoded the bitstream to obtain video information. Furthermore, the bitstream extractor is also transplanted into this system. The decoded video information is displayed on LCD monitor. To switch scalability function, we applied DIP switchs to separately enable temporal, spatial, SNR, and combine scalability.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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