本論文主要研究內容為Ka頻段射頻毫米波前端電路-低雜訊放大器之設計，所設計的晶片是利用TSMC 0.18 ?m CMOS製程研製。低雜訊放大器使用兩級疊接式架構來實現，前級針對低雜訊做匹配，後級則是以取得高增益為目標。電路在設計時加入一個串聯電感在共源極和共閘極電晶體之間來提高電晶體的fT值，進而使電路整體增益增加，雜訊減少。 所設計之晶片其量測結果如下，當總功率消耗為4.56 mW時，Ka頻段低雜訊放大器增益在29.1 GHz達到11.24 dB，雜訊指數為8.09 dB，輸入和輸出反射損耗在28 GHz皆大於7.1 dB。輸入1-dB壓縮點和三階截斷點在29 GHz分別為-25 dBm和-16 dBm。當總直流功耗為7.95 mW時，在29.4 GHz得到的小信號增益為16.5 dB，最小雜訊指數在28 GHz為6.92 dB，輸入和輸出反射損耗在28 GHz分別為5.35 dB和11.7 dB。晶片面積為0.66 × 0.93 mm2。 The subject of paper is to present the low noise amplifier of RF front-end circuits for Ka-band receiver being implemented on TSMC 0.18-μm CMOS technology. The low noise amplifier is implemented by a cascoding two stages. The first stage is designed for low noise performance while the second stage is matched for high gain. The circuit design by adding a series inductor between the CS and CG transistors to improve the transistors’ fT for increasing the circuit’s overall gain, and reducing the noise figure (NF). The measured results of the designed circuit are illustrated as follows: when the total DC power consumption is 4.56 mW, the Ka-band LNA achieve a gain of 11.24 dB at 29.1 GHz, noise figure of 8.09 dB, and the input/output return losses are more than 7.1 dB at 28 GHz. The input 1-dB power gain compression point (P1dB) and the input third-order interception point (IIP3) at 29 GHz occur at -25 dBm and -16 dBm, respectively. When the total DC power consumption is 7.95 mW, the obtained small signal gain is 16.5 dB at 29.4 GHz and minimum NF of 6.92 dB at 28 GHz. The input/output return losses are 5.35 dB and 11.7 dB at 28 GHz. The occupied chip area is 0.66 × 0.93 mm2.
