應用於Ka/V頻段低功率消耗及高線性度射頻前端接收機電路之研製; The Implementations of Low Power Consumption and High Linearity RF Front-End Receiving Circuits for Ka/V-Band Applications

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/25819

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/25819

Title:	應用於Ka/V頻段低功率消耗及高線性度射頻前端接收機電路之研製;The Implementations of Low Power Consumption and High Linearity RF Front-End Receiving Circuits for Ka/V-Band Applications
Authors:	陳柏寧;Po-ning Chen
Contributors:	電機工程研究所
Keywords:	低功率消耗;高線性度;接收機;high linearity;low power consumption
Date:	2010-01-21
Issue Date:	2010-06-11 16:20:53 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	本論文係以TSMC 0.18 μm 與TSMC 0.13 μm CMOS製程，研製應用於Ka頻段與V頻段射頻接收機前端電路。主要設計電路包含低雜訊放大器與雙平衡混頻器。低雜訊放大器部分，使用三級共源級放大器串接式架構來實現，第一級共源級放大器主要提供雜訊匹配以降低整體電路的雜訊指數，二三級則是利用電流密度來分析在雜訊與增益間取得平衡點。傳輸線是採用結合共平面波導與微帶線優點的最底層金屬當作地平面的共平面波導。此放大器量測增益在54.4 GHz有12.2 dB，雜訊指數4.7 dB，3-dB頻寬8.3 GHz，功率消耗8.8 mW，晶片面積0.35〖 mm〗^2。第二個高線性低雜訊放大器一樣採用三級共源級放大器串接實現，與前一個低雜訊放大器不同點是將第一級的偏壓在電流密度的雜訊最低點，藉此可得到較佳的雜訊指數，並且在第三級加入抑制三階非線性項的機制，可使得電路整體線性度提升，此電路的量測結果為增益在54.8 GHz有10.7 dB，雜訊指數3.7 dB，3-dB頻寬為9.7 GHz，在高線性的偏壓狀態僅消耗6.8 mW，晶片面積0.35 mm^2。雙平衡混頻器部分，首先應用在V頻帶的混頻器，電路中包含在LO端使用的堆疊式馬遜平衡器，比起變壓器能有較寬的頻寬，而且單轉雙可使得量測更為方便。混頻器本身則採用基極驅動而非傳統閘極驅動，此混頻器的工作電流很小，因此有優異的功率消耗，量測結果在64 GHz有3 dB的轉換損耗，輸入1-dB壓縮點為-5 dBm，輸入三階交互調變交叉點為5 dBm，混頻器本身僅需0.64 mW，晶片面積0.55〖 mm〗^2。Ka頻帶分別有傳統電流注入吉爾伯特混頻器與兩個基極驅動混頻器，傳統的吉爾伯特因為有電流注入的機制，可以在不影響整體增益下縮小由本地震盪控制的開關電晶體大小，因為藉此提升開關的切換速度與降低熱雜訊的注入，在轉導級與開關中間加入並聯電感共振寄生電容以提高電晶體操作頻率進而提高增益，量測結果在26 GHz有8.745 dB的轉換增益，輸入1-dB壓縮點為-16 dBm，輸入三階交互調變交叉點為-2 dBm，功率消耗18.46 mW，晶片面積0.61〖 mm〗^2。Ka頻帶的基極驅動混頻器，LO端一樣使用的堆疊式馬遜平衡器，量測結果在28.7 GHz有8.088 dB的轉換增益，輸入1-dB壓縮點為-14 dBm，輸入三階交互調變交叉點為-5 dBm，混頻器本身僅需0.31 mW，晶片面積0.828 mm^2。最後混頻器核心一樣是基極驅動，與上一個電路的差別在於在射頻端加入了前級放大器，此前級放大器採用共源級放大器以增加整體增益與降低整體的雜訊指數，電路中LO亦端使用的堆疊式馬遜平衡器單轉雙，量測結果在27 GHz有12.43 dB的轉換增益，輸入1-dB壓縮點為-17 dBm，輸入三階交互調變交叉點為-8.6 dBm，混頻器本身包含前級共源級放大器僅需2.5 mW，晶片面積0.82〖 mm〗^2。 The thesis presents RF front-end circuits for Ka/V-band receiver, the circuits are both implemented on TSMC 0.18 μm and TSMC 0.13 μm CMOS technologies. The implemented circuits include two V-band low noise amplifiers, a V-band doubly balanced mixer, and three Ka-band doubly balanced mixers. The LNAs include three cascade common source (CS) stages. In the two LNAs, the current density is used to decide transistor size and bias condition. The first stage of LNA is biased for the minimal noise figure (〖NF〗_min). The other stages are biased for the trade-off between the gain and NF. The grounded coplanar waveguide (GCPW) transmission line is used to shield the electrical and magnetic field from penetrating the substrate. The GCPW line has both advantages of microstrip line and coplanar wave-guide (CPW). LNA1 achieves a measured peak power gain of 12.2 dB at 54.4 GHz and only consumes a DC power of 8.8 mW. The measured NF of the LNA is 4.7 dB at 61 GHz, and 3-dB bandwidth is about 8.3 GHz. The chip size is only 0.35 mm^2. LNA2 is highly linear LNA. For the lowest 〖NF〗_min, the first stage of LNA2 is biased at current density of the lowest 〖NF〗_min. The other stages are biased at current density of the trade-off between gain and NF. The third stage CS amplifier with a third-order transconductance (g_m3) cancellation cell operates in parallel to compensate negative g_m3 value, and then it can enhance the linearity of LNA. The designed LNA achieves a measured peak power gain of 10.7 dB at 54.8 GHz. The measured NF of the LNA is 3.7 dB at 61 GHz. When g_m3 cancellation cell is biased at negative bulk-to-source voltage, the linearity of LNA would be better than 2 dBm and the power consumption is only 6.8 mW. The 3-dB bandwidth is about 9.7 GHz. The chip size is 0.35 mm^2. The V band mixer includes an LO stacked Marchand balun, and bandwidth of the balun is larger than transformer. Since RF and LO are single in, the measurement is simpler than fully differential one. The mixer core adopted a bulk-driven topology. Since the mixer core draw very few current, the mixer has very low power consumption. The designed mixer achieves a measured conversion gain of -3 dB at 64 GHz, and it consumes 0.644 mW. The input 1-dB compression point (IP1dB) is -5 dBm, and the input third-order intercept point (IIP3) is 5 dBm at 64 GHz. The chip size is 0.55 mm^2. The three Ka-band mixers are Gilbert cell mixer with current bleeding, bulk-driven mixer, and bulk-driven mixer. The traditional Gilbert cell mixer (Mixer A) with current bleeding technique can improve mixer noise and maintain the conversion gain. Furthermore, the inductors are added parallel between the switching stage, RF stage, and current bleeding to resonate out the total capacitance looking into the drain of RF stage to enhance conversion gain. The mixer achieves a measured conversion gain of 8.745 dB at 26 GHz, and it consumes 18.46 mW. The input 1-dB compression point is -16 dBm, and the IIP3 is -2 dBm at 26 GHz. The chip size is 0.65 mm^2. Mixer B is a bulk-driven mixer, it also includes an LO stacked Marchand balun. The peak conversion gain is 8.088 dB at RF frequency 28.7 GHz, and only needs very low power consumption of 0.3136 mW. The input 1-dB compression point is -14 dBm, and theIIP3 is -5 dBm at 28.7 GHz. The chip size is 0.828 mm^2. Final, mixer C compared to mixer A is added a common source in front of the mixer for the higher conversion gain and lower NF. It also includes an LO stacked Marchand balun. The peak conversion gain is 12.43 dB at RF frequency of 27 GHz, and only need very low power consumption of 2.505 mW. The input 1-dB compression point of -17 dBm, and the IIP3 is -8.6 dBm at 27 GHz. The chip size is 0.82 mm^2.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	805	View/Open

社群 sharing

Loading...