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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/29267


    Title: Decentralized BIST methodology for system level interconnects
    Authors: Su,CC;Jou,SJ
    Contributors: 電機工程研究所
    Date: 1999
    Issue Date: 2010-06-29 20:20:25 (UTC+8)
    Publisher: 中央大學
    Abstract: This paper presents an architecture for the local generation of global test vectors for interconnects in a multiple scan chain environment. A unified BIST module is inserted as the gateway for each scan chain to transform the hierarchy of backplane, boards, and scan chains into a one-dimensional array of scan chains. The BIST modules are identical for all the scan chains except for the programmable personalized memories. The personalized memory contains a scan stage type table for the test generation, response compression, and driver contention avoidance. It also contains a scan chain identification number which serves as the seed for the generation of globally distinct serial vectors. The proposed methodology achieves 100% coverage on stuck-at and short faults.
    Relation: JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
    Appears in Collections:[電機工程研究所] 期刊論文

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