An automatic gain control architecture for SONET OC-3 VLSI

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題名:	An automatic gain control architecture for SONET OC-3 VLSI
作者:	Wang,CK;Huang,PC
貢獻者:	電機工程研究所
日期:	1997
上傳時間:	2010-06-29 20:20:59 (UTC+8)
出版者:	中央大學
摘要:	This brief presents a synchronized feedback-type automatic gain control (AGC) architecture for SONET (synchronous optical network) OC-3 system which is suitable for scaled BJT or CMOS VLSI implementation, In this architecture, a second-order loop is utilized instead of a conventional loop, and a convenient methodology is presented for calculating the parameters of the AGC. Simulation results using micromodels in the HSPICE environment indicate that for a 20 dB dynamic range of input 77.76 MHz sinusoidal signal, the architecture yields an 80 kHz loop bandwidth and a constant 1 V-pp output magnitude.
關聯:	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING
顯示於類別:	[電機工程研究所] 期刊論文

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