CLEAVAGE FRACTURE UNDER TENSION WITH CONSTRAINT

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題名:	CLEAVAGE FRACTURE UNDER TENSION WITH CONSTRAINT
作者:	JOU,SJ;CHIOU,SH;TAO,YS;SHEN,WZ
貢獻者:	電機工程研究所
關鍵詞:	CIRCUITS
日期:	1993
上傳時間:	2010-06-29 20:24:47 (UTC+8)
出版者:	中央大學
摘要:	An efficient simulator of multiple sets of multiple faults, with electrical timing information for an MOS IC. is presented. The physical faults in a real circuit are modelled more realistically by the node-short, line-open and threshold voltage degradation faults at the transistor level. On using event-driven, selective trace and mixed incremental-in-space. signal and time simulation techniques. the simulation results show that it is superior to other approaches in speed, extra memory used, and precision. Moreover, this simulator is suitable for parallel simulation in a multiprocessor system.
關聯:	IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS
顯示於類別:	[電機工程研究所] 期刊論文

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