SYNTHESIZING NESTED LOOP ALGORITHMS USING NONLINEAR TRANSFORMATION METHOD

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > journal & Dissertation > Item 987654321/29483

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/29483

Title:	SYNTHESIZING NESTED LOOP ALGORITHMS USING NONLINEAR TRANSFORMATION METHOD
Authors:	SHEU,JP;CHANG,CY
Contributors:	電機工程研究所
Keywords:	PARALLEL PROCESSOR BOUNDS;FORTRAN-LIKE LOOPS;TIME
Date:	1991
Issue Date:	2010-06-29 20:25:54 (UTC+8)
Publisher:	中央大學
Abstract:	In this paper, we synthesize nested For-loops with partitions on the innermost loop. First, we present a nonlinear transformation algorithm to exploit the parallelism of the For-loops. By the mapping of nonlinear transformation, iterations of For-loops can be executed in a parallel form. The proposed algorithm is useful in exploiting the parallelism of For-loops with one or more partitions on the innermost loop. Then, we also design algorithms to partition and map the nested For-loops onto the fixed size systolic arrays. Based on the time and space mapping schemes, all the iterations of For-loops can be correctly executed on the array processors in a parallel form.
Relation:	IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS
Appears in Collections:	[Graduate Institute of Electrical Engineering] journal & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	484	View/Open

社群 sharing