A built-in redundancy-analysis scheme for random access memories with two-level redundancy

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Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/31754

Title:	A built-in redundancy-analysis scheme for random access memories with two-level redundancy
Authors:	Chang,Da-Ming;Li,Jin-Fu;Huang,Yu-Jen
Contributors:	電機工程研究所
Keywords:	2-D REDUNDANCY;SELF-TEST;REPAIR;RAMS
Date:	2008
Issue Date:	2010-07-06 18:10:50 (UTC+8)
Publisher:	中央大學
Abstract:	Built-in self-repair (BISR) technique is a popular method for repairing defective embedded memories. To allocate redundancy efficiently, built-in redundancy-analysis (BIRA) component is a core component in a BISR design. This paper presents a BIRA scheme
Relation:	JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS
Appears in Collections:	[Graduate Institute of Electrical Engineering] journal & Dissertation

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